The disclosure provides a method for fabricating a low resistance contact on a semiconductor substrate comprising a metal oxide semiconductor (MOS) device. The method comprises fabricating a via to a source or drain region of the MOS device, providing an insulating layer along a sidewall of the via while maintaining or reestablishing the exposed source or drain region, using ion implantation to implant a metallic element into the exposed source or drain region of the semiconductor substrate through the via to form an implanted layer, annealing the implanted layer to form a silicide layer comprising silicon and the metallic element on the source or drain region of the MOS device, and depositing a low resistance metal in the via to form the low resistance contact on the semiconductor substrate comprising the MOS device. The disclosure also provides a device comprising a low resistance contact fabricated by said method.

A semiconductor device comprises a first conductive layer, a first semiconductor element bonded to one side in a first direction of the first conductive layer, a first power terminal conductive to the first conductive layer and the first semiconductor element, a first sealing resin covering the first conductive layer and the first semiconductor element, and a first extension terminal conductively bonded to the first power terminal. The first power terminal has a first exposed portion exposed from the first sealing resin. The first extension terminal is conductively bonded to the first exposed portion.

An electronic device and a manufacturing method thereof are provided. The manufacturing method includes: providing a first portion, where the first portion includes a first substrate, active devices formed by a semiconductor epitaxial structure grown on the first substrate, and a first bonding structure formed over the first substrate and electrically coupled to the active devices; providing a second portion, where the second portion is free of active devices and the second portion includes a second substrate, passive devices formed over the second substrate, and a second bonding structure electrically coupled to the passive devices; and forming a signal processing circuit by bonding the first portion to the second portion, where the active devices are electrically coupled to the passive devices by bonding the first bonding structure to the second bonding structure to form the signal processing circuit.

The present disclosure discloses a package including a first support portion, a second support portion, and multiple pins. The first support portion includes a first upper metal layer and a first lower metal layer, wherein the first lower metal layer is connected to and overlaps with the first upper metal layer, corresponding to the position of the first upper metal layer. The second support portion is laterally separated from the first support portion, and the second support portion includes a second metal layer. The multiple pins are laterally separated from the first support portion and the second support portion, where in a top view, a ratio of a maximum length of the second metal layer to a maximum length of the package is greater than .

A semiconductor device includes a support substrate, a semiconductor element, and a sealing resin. The support substrate includes a support surface facing a first side in the thickness direction and a bottom surface facing a second side in the thickness direction. The semiconductor element is disposed on the support surface. The sealing resin covers the semiconductor element and a portion of the support substrate. The bottom surface is exposed from the sealing resin and includes a grinding trace. The sealing resin includes a resin obverse surface facing the first side in the thickness direction and a first resin reverse surface facing the second side in the thickness direction. The first resin reverse surface surrounds the bottom surface as viewed in the thickness direction and is located on the first side in the thickness direction relative to the bottom surface.

A semiconductor device, including: a substrate having a mounting surface; a semiconductor element mounted on the mounting surface of the substrate; and a positive electrode terminal and a negative electrode terminal disposed on the substrate. Each of the positive electrode terminal and the negative electrode terminal has at least one rising portion, to thereby have a total of at least three rising portions, each extending in a plane that intersects the mounting surface of the semiconductor element. Each of the rising portion of the positive electrode terminal faces one of the rising portions of the negative electrode terminal in a first direction.

In an electronic module, electrode pads of a first circuit component and electrode pads of a second circuit component are arranged such that conductive bonding members disposed between the electrode pads of the first circuit component and the electrode pads of the second circuit component form bonding member groups, each of which includes two or more conductive bonding members arranged along one direction in a plane direction of the first circuit component, with the one direction being defined as an extension direction of each of the bonding member groups. Each of reinforcing members is disposed apart from an adjacent bonding member group among the bonding member groups, and each of the reinforcing members has a first portion that extends along a direction intersecting with the extension direction of the adjacent bonding member group, and a second portion that extends along the extension direction of the adjacent bonding member group.

A semiconductor device includes a conductive layer, a first semiconductor element having a first gate electrode, a second semiconductor element having a second gate electrode, and a first signal terminal electrically connected to the first gate electrode and the second gate electrode. The first signal terminal has a first contact point. Let L1 denote a length of a straight line connecting a first center of the first gate electrode and the first contact point. Let L2 denote a length of a straight line connecting a second center of the second gate electrode and the first contact point. Let R1 denote a first conductive-path length from the first center to the first contact point. Let R2 denote a second conductive-path length from the second center to the first contact point. Then, R2/R1 is closer to 1 than L2/L1 is.

According to an embodiment, a semiconductor device includes a semiconductor chip having a first surface on which a source electrode and a gate electrode are provided and a second surface that is opposed to the first sur face and on which a drain electrode is provided, a source terminal having a fourth surface exposed from a third surface of a package and a fifth surface coupled to the source electrode and having a shape different from a sha pe of the fourth surface, a gate terminal having a sixth surface exposed from the third surface of the package and a seventh surface coupled to the gate electrode and having a shape different from a shape of the sixth surface, and a drain terminal coupled to the drain electrode and having an eighth surface exposed from the third surface of the package.

A semiconductor device includes: a conductive layer including a mounting surface; a first semiconductor element bonded to the mounting surface; a first terminal electrically connected to the first semiconductor element; and a first bonding layer electrically bonding the conductive layer and the first terminal. The conductive layer includes a first end surface, and a first peripheral surface located inward of the conductive layer from the first end surface as viewed in a first direction. The conductive layer includes a first engagement portion defined by the first peripheral surface. The first terminal includes a first bonding portion electrically bonded to the first engagement portion via the first bonding layer. As viewed in the first direction, the first bonding portion overlaps with the first engagement portion.