A hybrid power phase leg includes a phase node, a heatsink, a first semiconductor switch, and a second semiconductor switch. The first semiconductor switch includes a first cooling side, a first power node that neighbors the first cooling side, and a first switching node. The first cooling side is thermally connected to the heatsink and the first switching node is electrically connected to the phase node. The first switching node pulls the phase node toward a positive voltage rail while in a conductive state. The second semiconductor switch includes a second cooling side, a second power node that neighbors the second cooling side, and a second switching node. The second cooling side is thermally connected to the heatsink and the second switching node is electrically connected to the phase node. The second switching node pulls the phase node toward a negative voltage rail while in the conductive state.

A stack includes a first power semiconductor device in a first chip and a second power semiconductor device in a second chip. The first power semiconductor device is configured for active operation during which an application load current is conducted by the first power semiconductor device and power losses occur in the first power semiconductor device. The second power semiconductor device is configured for passive operation during which a voltage is blocked. The stack further includes a heat sink interface configured to dissipate the power losses. The second chip is arranged between the first chip and the heat sink interface.

Provided is a semiconductor device that can suppress deterioration of assemblability and can achieve downsizing. The semiconductor device includes a base member, a first semiconductor element, and a second semiconductor element. The second semiconductor element has a planar size smaller than that of the first semiconductor element. The first semiconductor element and the second semiconductor element are arranged in a first direction. In the base member, a first groove is formed to surround the first semiconductor element, a second groove is formed to surround the second semiconductor element. The first groove and the second groove overlap each other in a region between the first semiconductor element and the second semiconductor element. In a second direction, a distance between portions of the second groove disposed to sandwich the second semiconductor element is smaller than a distance between portions of the first groove disposed to sandwich the first semiconductor element.

An electronic module, including: a first conductive plate which contains copper or a first copper alloy as a main component thereof; a second conductive plate which has a main surface that faces the first conductive plate and has a side surface that extends continuously from the main surface, and which contains copper or a second copper alloy as a main component thereof; and a first metal oxide layer which is provided on the main surface and the side surface of the second conductive plate, and which contains a first metal oxide that is of a metal different from a metal of the second conductive plate and is electrically insulating.

A semiconductor device according to an embodiment has a circuit board having a first surface facing a first side, and a second surface facing a second side on a side opposite to the first side. The semiconductor device has a chip mounted on the first surface. The semiconductor device has a heat transfer member joined to the second surface with a first joint layer therebetween. The semiconductor device has a heat dissipation member joined to a surface of the heat transfer member facing the second side with a second joint layer therebetween. Each of the first joint layer and the second joint layer is a sintered body.

A semiconductor device according to various embodiments includes a substrate and a plurality of transistor stacks formed on the substrate. Each of the transistor stacks includes a lower transistor including at least one lower channel layer and a lower gate structure enclosing the at least one lower channel layer and formed on the substrate, and an upper transistor including at least one upper channel layer and an upper gate structure enclosing the at least one upper channel layer and formed on the lower transistor. A sum of a number of first lower channel layers and a number of first upper channel layers of a first transistor stack is different from a sum of a number of second lower channel layers and a number of second upper channel layers of a second transistor stack.

The n/p MOS gate stack includes a semiconductor substrate having an nMOS region and a pMOS region, an nMOS stack including a first interface layer, a first high dielectric layer formed on the first interface layer, a first n-metal layer formed on the first high dielectric layer, and a first upper electrode formed on the first n-metal layer, which are formed in the nMOS region, and a pMOS stack including a second interface layer, a second high dielectric layer formed on the second interface layer, a second p-metal layer formed on the second high dielectric layer, a second n-metal layer formed on the second p-metal layer, and a second upper electrode formed on the second n-metal layer, which are formed in the pMOS region. The first high dielectric layer includes a first dipole material, and the second p-metal layer includes a second dipole material.

A semiconductor package is provided. The semiconductor package may include a housing; a semiconductor chip, disposed within the housing; a top connector, connected to the semiconductor chip; a leadframe, coupled to the top connector; and a temperature sensor chip, disposed on the top connector.

An electric circuit body includes a semiconductor device incorporating a semiconductor element by sealing with a sealing material and having a heat dissipating surface for dissipating heat of the semiconductor element, the heat dissipating surface being formed on at least one surface, a cooling member disposed facing the heat dissipating surface of the semiconductor device and configured to cool the semiconductor element, and a heat conduction member disposed between the semiconductor device and the cooling member, wherein a terminal connected to the semiconductor element protrudes out from at least one side surface of the semiconductor device, and a first interval between the sealing material and the cooling member on the one side surface of the semiconductor device from which the terminal is protruded is narrower than a second interval between the sealing material and the cooling member on the other side surface of the semiconductor device from which the terminal is not protruded.

A High Electron Mobility Transistor, (HEMT), structure having a gate, a source and a drain, the HEMT structure including a depletion-mode transistor having a breakdown voltage, current limiting means arranged for ensuring that a drain source current of the HEMT structure, in an off-state of the HEMT structure, is at most 20 nA/mm, being a current per unit gate length of the depletion-mode transistor, the HEMT structure can include just the depletion-mode transistor or a cascode configuration of a depletion-mode transistor with an enhancement mode transistor.