A semiconductor device includes: a first substrate including first front side pads arranged around a front surface; a second substrate including second front side pads arranged around a front surface; a third substrate; first connection members each electrically connecting a corresponding first front side pad on the first substrate and a corresponding third back side pad on the third substrate; second connection members each electrically connecting a corresponding second front side pad on the second substrate and a corresponding third front side pad on the third substrate; a first resin layer that is in contact with a periphery of the front surface of the first substrate and a periphery of the back surface of the third substrate; and a second resin layer that is in contact with a periphery of the front surface of the second substrate and a periphery of the back surface of the third substrate.

A first gate pattern and a first source pattern are linearly formed in parallel to each other along a first edge of an insulating substrate. A second gate pattern is formed in a quadrangular shape in a top view, extending from the first edge side of the insulating substrate to a second edge side facing the first side. A drain pattern is formed to surround at least three edges of the quadrangular shape of the second gate pattern. A second source pattern is formed along an edge other than the first edge of the insulating substrate to surround the drain pattern. First and second semiconductor chip groups are arranged at positions adjacent to the second source pattern. The first and second semiconductor chip groups and the second source pattern are connected via a plurality of first source wires.

The present disclosure provides a semiconductor power module. The semiconductor power module includes a first substrate, a second substrate, and a plurality of switch bars stacked and laterally positioned between the first substrate and the second substrate. Each switch bar includes a plurality of dies disposed in parallel, each die of the plurality of dies comprising a switch device with a source, a drain, and a gate, a gate driver printed circuit board (PCB) connected to the gates of the switch devices in the plurality of dies, and interconnects configured to connect the sources and drains of the switch devices in the plurality of dies. The switch devices of the same switch bar are electrically connected in parallel and respective switch devices of different switch bars are electrically connected in series.

Without causing characteristic variations in paired elements, the increase in development cost and development period is suppressed. A plurality of MOS units 30 are arranged adjacent to each other on a main surface of a semiconductor substrate in a plan view, each of the plurality of MOS unit is comprised of at least one MOSFET and has same structure. Above the plurality of MOS units 30, a multilayer wiring layer is formed. In an uppermost wiring layer of the multilayer wiring layer, wiring M8 is formed. Each of the plurality of MOS units 3Q includes MOS unit 10 and MOS unit 20, which constitute a part of the differential circuit as paired elements. The coverage rate of MOS unit 10 covered by wiring M8 is the same as the coverage rate of MOS unit 20 covered by wiring M8 in the plan view.

According to one embodiment, a semiconductor apparatus includes: a wiring board having a first through-hole; a first substrate including a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer, the first substrate being provided in the first through-hole; a first semiconductor chip provided on the first substrate in the first through-hole; and a sealing member that covers the first substrate and the first semiconductor chip in the first through-hole, wherein a first dimension of the first insulating layer in a first direction parallel to a surface of the first substrate is larger than a second dimension of the first conductive layer in the first direction and a third dimension of the second conductive layer in the first direction.

A semiconductor device, including: a semiconductor chip; an insulated circuit substrate that has: a metal plate including a ground region on an upper surface thereof, an insulating layer disposed on the upper surface of the metal plate with the ground region exposed therefrom, and a conductive circuit pattern plate on which the semiconductor chip is mounted; a ground wiring member conductively connected to the ground region of the metal plate, the ground wiring member being conductive and including an upper end portion located above the insulated circuit substrate; and a sealing member sealing the semiconductor chip, the insulated circuit substrate and the ground wiring member, the sealing member having a sealing upper surface and including an opening formed therein to expose therethrough the upper end portion of the ground wiring member above the insulated circuit substrate.

According to one embodiment, a semiconductor device includes first and second circuit boards, a first semiconductor chip, a first column and a first terminal. The second circuit board is provided above the first circuit board. The first semiconductor chip is provided between the first and second circuit boards. The first column is provided between the first and second circuit boards. The first terminal is provided at an end of the first circuit board in a first direction, and has a first cut. The first cut of the first terminal has a first part, a second part, and a third part. The first part extends from an end of the first terminal in the first direction. The second part is continuous with the first part and extends in a second direction crossing the first direction. The third part is continuous with the second part and extends in the first direction.

According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of electrode films and a plurality of first insulating films are alternately stacked in a first direction, a columnar body that penetrates the stacked body in the first direction, an aluminum oxide film provided between the columnar body and each of the electrode films, and a first tetravalent metal oxide provided at an interface between the columnar body and the aluminum oxide film.

A first semiconductor chip has a first surface in contact with a first circuit board and a second surface on which a second conductor is provided. A second semiconductor chip has a third surface in contact with a second circuit board and a fourth surface on which a third conductor is provided. A first pillar has a fifth surface in contact with the first circuit board. A second circuit board is in contact with a surface of a second conductor, a surface of a third conductor, and the first pillar. A plurality of insulating pillars extends in a direction connecting the first and second circuit boards and are in contact with the first and second circuit boards. A sealing body surrounds the first and second semiconductor chips, the first pillar, and the insulating pillars, and includes.

A semiconductor device includes first semiconductor chips that each include a first control electrode and a first output electrode, second semiconductor chips each include a second control electrode and a second output electrode, first and second input circuit patterns on which the first and second input electrodes are disposed, respectively, first and second control circuit patterns electrically connected to the first and second control electrodes, respectively, first and second resistive elements, and a first inter-board wiring member. The first control electrodes and first resistive element are electrically connected via the first control circuit pattern, the second control electrodes and second resistive element are electrically connected via the second control circuit pattern, and at least one of the first output electrodes and at least one of the second output electrodes are electrically connected to each other via the first inter-board wiring member.