A manufacturing method of a semiconductor device capable of improving the accuracy of overcurrent detection is provided. The manufacturing method of a semiconductor device includes a semiconductor wafer testing process includes a first testing process to determine the resistance variation rate of the replica resistor due to manufacturing variations when manufacturing the semiconductor wafer, and a setting process to determine the variation value of the reference current based on the resistance variation rate determined in the first testing process and set the current value of the current circuit to reduce the variation value.

A semiconductor device includes: a first semiconductor element; a first terminal positioned on a first side in a first direction relative to the first semiconductor element; a protective layer of an insulator partially covering the first semiconductor element; and a first conductive member electrically connected to the first semiconductor element and the first terminal. The protective layer is spaced apart from the first terminal. The first conductive member is positioned between the first semiconductor element and the first terminal in the first direction. The first conductive member includes a first portion overlapping with the protective layer as viewed in a direction perpendicular to the first direction, and a second portion connected to the first portion and positioned on a side opposite the first semiconductor element with respect to the first portion. The second portion protrudes from the protective layer as viewed in a direction perpendicular to the first direction.

The present disclosure relates to a power semiconductor module including: a carrier; a plurality of semiconductor dies mounted onto the carrier; a housing including a frame enclosing the carrier circumferentially; a first external connection electrically connected to a first subset of the semiconductor dies, the first external connection protruding laterally from the housing at a first level; and an insert including an electrically isolating material and a second external connection mounted onto the electrically isolating material. The insert is at least partially mounted to the frame and at least partially covers the carrier and/or the first subset of the plurality of semiconductor dies. The second external connection is connected to a second subset of the plurality of semiconductor dies. The second external connection protrudes from the housing.

The present invention is directed to a power supply module for immersion cooling, by providing uneven edges between the edge of the metal layer of the upper surface and the lower surface of the third substrate and the edge of the third substrate, the design of the spacing between adjacent metal layers and the design of the height of the gap between the third substrate and the first substrate or the second substrate, the faults and failures caused by the conductive particles in the cooling fluid are reduced. On the other hand, by dispensing glue at the key position between the first substrate and the third substrate and between the second substrate and the third substrate, the possibility that the conductive particles fluid into the power supply module is further reduced. The present invention further discloses several structures and manufacturing processes of the third substrate for immersion cooling.

A semiconductor device includes a first conductive portion, a second conductive portion, a first semiconductor element, a second semiconductor element, two first terminals, a second terminal, a third terminal, a first conductive member, a second conductive member, a plurality of first control terminals, a plurality of second control terminals, and a sealing resin. In a first direction orthogonal to the thickness direction, the first conductive portion and the second conductive portion are spaced apart from each other. The second terminal and the second conductive member form a conduction path located outside the plurality of first control terminals in a second direction orthogonal to the thickness direction and the first direction.

The present disclosure proposes a semiconductor device, as well as a method for manufacturing such a semiconductor device, and related to a method of generating a dual exposed drain with common gate and source clip-bonded package for reverse battery protection. The semiconductor device includes a first lead frame with an external first lead frame terminal and a first die paddle, a second lead frame with an external second lead frame terminal and a second die paddle, a common clip with an external source clip terminal, a two source contacts, a common gate clip with an external common clip gate terminal, a clip contact and a gate clip contact, a first semiconductor die with a first die gate terminal, a first die source terminal, and a first die drain terminal, a second semiconductor die with a second die gate terminal, a second die source terminal, and a second die drain terminal.

An electronics assembly includes a motherboard, a processor, and a z-axis power delivery (ZPD) module. The processor is mounted on the motherboard. The ZPD module is electrically connected to a substrate of the processor through an opening that goes all the way through the motherboard. The processor may be a central processing unit (CPU), a graphics processing unit (GPU), or a system-on-a-chip (SOC), for example.

A cooling apparatus for a power module is provided. The cooling apparatus includes: a power module including power element chips, and a circuit substrate bonded to the power element chips; a heat sink in contact with the circuit substrate, the heat sink having through-holes formed therein; and a manifold configured to allow cooling fluid to flow therethrough and including a wall portion in contact with the circuit substrate. The wall portion includes at least two or more extended ends that extend in a flow direction of the cooling fluid, and a closed end connected to each of the extended ends. The extended ends partly or completely overlap the power element chips.

A semiconductor device includes: a switch circuit chip and a control circuit chip, which are mounted on a first die pad; a first conductive bonding material configured to bond the first die pad and the switch circuit chip; and a second conductive bonding material configured to bond the first die pad and the control circuit chip. The switch circuit chip includes: a first semiconductor substrate bonded to the first die pad by the first conductive bonding material; and a first transistor and a second transistor, which have sources connected to each other. Both the first transistor and the second transistor are high electron mobility transistors including nitride semiconductors. The source of the first transistor and the source of the second transistor are electrically connected to the first die pad via the control circuit chip.

A semiconductor device includes: a substrate with a circuit pattern: a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern; a frame member including a wall portion; and a plate-shaped terminal electrically connected to the circuit pattern. The wall portion surrounds the substrate. The terminal includes a first region attached to the wall portion, and a second region continuous to the first region and located inside the frame member. A distance between an inner wall surface of the wall portion and the circuit pattern is 500 m or less. The second region is directly connected to the circuit pattern.