Provided is a semiconductor device which includes: a 1.sup.st transistor including a 1.sup.st channel structure extended in a 1.sup.st direction, and a 1.sup.st gate structure on the 1.sup.st channel structure; a 2nd transistor comprising a 2.sup.nd channel structure extended in the 1.sup.st direction, and a 2.sup.nd gate structure on the 2.sup.nd channel structure, the 2.sup.nd transistor being disposed adjacent to the 1.sup.st transistor in a 2.sup.nd direction that horizontally intersects the 1.sup.st direction; a 1.sup.st isolation wall between the 1.sup.st channel structure and the 2.sup.nd channel structure; and a 1.sup.st gate cut structure between the 1.sup.st gate structure and the 2.sup.nd gate structure on the 1.sup.st isolation wall in a 3.sup.rd direction that vertically intersects the 1.sup.st direction and the 2.sup.nd direction.

A monolithic 3D complementary field-effect transistor (FET) (CFET) circuit includes a first CFET structure and a second CFET structure in a logic circuit within a device layer. A first interconnect layer disposed on the device layer provides first and second input contacts and an output contact of a logic circuit. Each CFET structure includes an upper FET having a first type (e.g., P-type or N-type) on a lower FET having a second type (e.g., N-type or P-type). The FETs in the monolithic 3D CFET circuit may be interconnected to form a two-input NOR circuit or a two-input NAND circuit. Vertical access interconnects (vias) may be formed within the device layer to interconnect the FETs externally and to each other. The FETs may be formed as bulk-type transistors or SOI transistors.

A semiconductor device may include a substrate, a lower power line in a lower portion of the substrate, metal layers on the substrate, and a protection structure that is electrically connected to the lower power line and the metal layers. The protection structure may include a doping pattern in the substrate, and a first source/drain pattern that is on the substrate and is electrically connected to an upper portion of the doping pattern. The doping pattern and the first source/drain pattern may include different dopants from each other.

A method includes receiving a structure including a first region and a second region, forming a dielectric layer over the first region and the second region, forming a first patterned layer of a first dipole material on the dielectric layer in the first region, performing a first thermal drive-in operation to drive the first dipole material into the dielectric layer, forming a second patterned layer of a second dipole material on the dielectric layer in the second region, performing a second thermal drive-in operation to drive the second dipole material into the dielectric layer, performing a thermal operation to adjust distribution of the first dipole material or both the first and the second dipole materials in the dielectric layer, and forming a gate electrode layer over the dielectric layer. A portion of the first region overlaps with the second region.

A semiconductor device is provided, the semiconductor device including: a first transistor and a second transistor on a substrate, wherein each of the first transistor and the second transistor includes an active pattern on the substrate, channel layers spaced apart from each other on the active pattern, and a gate dielectric layer and a gate electrode surrounding the channel layers, wherein the gate dielectric layer of the first transistor includes a first work function metal layer and a first work function adjusting layer on the first work function metal layer, and the gate electrode of the second transistor includes a second work function metal layer, the first and second work function metal layers include the same material, and the first work function adjusting layer includes an oxide of the same material, wherein a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor.

A semiconductor device includes channel members vertically stacked, a gate dielectric layer wrapping around each of the channel members, a first work function (WF) layer disposed over the gate dielectric layer and wrapping around each of the channel members, a first WF isolation layer disposed over the first WF layer, a second WF layer disposed over the first WF isolation layer, a second WF isolation layer disposed over the second WF layer, and a metal fill layer disposed over the second WF isolation layer. The first WF layer has a uniform thickness. The second WF isolation layer is a nitride-containing layer.

Disclosed is a semiconductor device comprising a first channel structure extending in a first direction, a second channel structure adjacent in a second direction to the first channel structure, a source/drain structure between the first and second channel structures including lower and upper source/drain patterns, and a lower contact that is in contact with the lower source/drain pattern. The lower source/drain pattern includes a first semiconductor layer and a second semiconductor layer in contact therewith. The first semiconductor layer has a sidewall in contact with the second semiconductor layer, a contact surface in contact with the lower contact, and a bottom surface that extends from the sidewall to the contact surface. The sidewall of the first semiconductor layer includes a first portion in contact with the second semiconductor layer, and a second portion spaced apart from the second semiconductor layer.

A semiconductor device includes a plurality of power lines disposed on a substrate. The power lines are arranged in a first direction and extended in a second direction and run parallel to each other. A first single height cell and a second single height cell are arranged in the first direction on the substrate. A first tap cell and a second tap cell are arranged in the first direction on the substrate. A power delivery network layer is disposed below the substrate. A first active pattern and a second active pattern are disposed between the power lines to be spaced apart from each other in the first direction. A first width of the first active pattern on the first single height cell is larger than or equal to a second width of the first active pattern on the first tap cell, when measured in the first direction.

A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.

A semiconductor device includes: first fins (F-fins) and second fins (S-fin) arranged in a first row having a single-row height and that includes an alpha cell region and a beta cell region. The alpha cell region includes a first F-fin, a first S-fin and a first gate structure overlapping each of the first F-fin and the first S-fin. The first gate structure does not overlap top and bottom edges of the alpha cell region. The beta cell region includes second and third F-fins, second and third S-fins and a second gate structure overlapping each of the second F-fin and second S-fin and at least one of the third F-fin or the third S-fin. A top edge of the beta cell region being co-track aligned with the third F-fin. A bottom edge of the beta cell region being co-track aligned with the third S-fin.