The disclosure relates to a complementary field effect transistor, CFET, structure. The CFET structure comprises: a first CFET element which is arranged in a first row of the CFET structure; and a second CFET element which is arranged in a second row of the CFET structure, wherein the second row is arranged laterally offset to the first row; wherein the first and the second CFET element each comprise: a first transistor structure, and a second transistor structure which is arranged above the first transistor structure. The CFET structure further comprises a shared signal routing structure which is arranged between the first and the second CFET element; wherein the shared signal routing structure is electrically connected to the first and/or the second transistor structure of the first and/or of the second CFET element, respectively.

A method of forming a semiconductor device includes depositing a target metal layer in an opening. Depositing the target metal layer comprises performing a plurality of deposition cycles. An initial deposition cycle of the plurality of deposition cycles comprises: flowing a first precursor in the opening, flowing a second precursor in the opening after flowing the first precursor, and flowing a reactant in the opening. The first precursor attaches to upper surfaces in the opening, and the second precursor attaches to remaining surfaces in the opening. The first precursor does not react with the second precursor, and the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.

Disclosed is a semiconductor device comprising a first channel region, a first dielectric structure on the first channel region, a first metal pattern spaced apart from the first dielectric structure, and a first dipole structure between the first metal pattern and the first dielectric structure. The first dipole structure includes a first dipole layer and a second dipole layer. The first dipole layer includes a first dipole element. The second dipole layer includes a second dipole element different from the first dipole element. A maximum oxidation number of the first dipole element is different from a maximum oxidation number of the second dipole element.

An integrated circuit includes first and second dummy gates extending in a second direction transverse to a first direction, a gate extending in the second direction and arranged between the first and second dummy gates, a first connection layer over the gate and the first and second dummy gates, a second connection layer over the first connection layer, and first and second via-connectors. The first connection layer includes first and second conducting lines extending in the first direction. The second connection layer includes third and fourth conducting lines extending in the second direction. The first via-connector is arranged between and connects the first and third conducting lines. The second via-connector is arranged between and connects the second and fourth conducting lines. The third conducting line overlaps the first dummy gate in a third direction transverse to both the first direction and the second direction.

An integrated circuit includes plural standard cells performing a same function. The standard cells include a first standard cell and a second standard cell, and the first standard cell and the second standard cell are to the same as each other in terms of an arrangement of internal conductive patterns and are different from each other in terms of a position of a via formed over a gate line through which an input signal is input.

In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers is formed, an isolation insulating layer is formed so that the stacked layer are exposed from the isolation insulating layer, a sacrificial cladding layer is formed over at least sidewalls of the exposed stacked layer, a sacrificial gate electrode is formed over the exposed stacked layer, an interlayer dielectric layer is formed, the sacrificial gate electrode is partially recessed to leave a pillar of the remaining sacrificial gate electrode, the sacrificial cladding layer and the first semiconductor layers are removed, a gate dielectric layer wrapping around the second semiconductor layer and a gate electrode over the gate dielectric layer are formed, the pillar is removed, and one or more dielectric layers are formed in a gate space from which the pillar is removed.

A method includes forming a multi-layer stack including a plurality of semiconductor nanostructures. The multi-layer stack includes a semiconductor nanostructure, and a sacrificial semiconductor layer over the semiconductor nanostructure. The method further includes depositing a semiconductor layer over and contacting the semiconductor nanostructure, removing the sacrificial semiconductor layer, and forming a replacement gate stack encircling a combined region of the semiconductor nanostructure and the semiconductor layer.

A semiconductor structure is provided. The semiconductor structure includes a first set of nanostructures that are stacked vertically and spaced apart from one another and formed in a first well, a source/drain feature adjoining the first set of nanostructures, a first top gate electrode layer above a topmost nanostructure in the first set of nanostructures, and an inner gate electrode layer sandwiched between the nanostructures. A first dimension of the inner gate electrode layer in a first direction is greater than a second dimension of the first top gate electrode layer in the first direction.

A method includes forming a p-type transistor. The method includes forming a gate dielectric on a semiconductor region, and depositing a p-type work-function layer on the gate dielectric. The p-type work-function layer includes a metal nitride, which includes a first metal and a second metal. An n-type work-function layer is deposited over the p-type work-function layer. A p-type source/drain region is formed aside of the semiconductor region.

A method for forming an integrated circuit device, the method comprising: forming a stack of field effect transistors, FETs, comprising a bottom FET and a top FET; forming a first trench underneath the bottom FET; forming a first hole, between the first trench and a first source/drain region of the bottom FET; forming a second hole, between the first hole and a contact of a contact layer arranged above the top FET; performing a first metal deposition to fill the first hole; the second hole; and part of the first trench, with metal; recessing the metal deposited in the first metal deposition; forming an isolation layer below the recessed metal; performing a second metal deposition to fill the first trench with metal, thereby forming a first backside wiring line in the first trench.