Provided is a semiconductor device that includes a first active pattern and a second active pattern on a substrate, the first active pattern spaced apart from the second active pattern in a first direction, and extending in a second direction, the second direction being different from the first direction, a lower channel pattern and a lower source/drain pattern on the first active pattern and alternately arranged in the second direction, an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern, a gate pattern on first active pattern, the lower channel pattern, and the upper channel pattern, and a first active contact connected to the lower source/drain pattern, and a second active contact connected to the upper source/drain pattern.

A semiconductor device includes: a substrate; source/drain patterns on the substrate; a channel pattern between the source/drain patterns, the channel pattern including a plurality of semiconductor patterns; a gate electrode between the plurality of semiconductor patterns; an upper separation structure extending in a first direction and spaced apart from the gate electrode in a second direction intersecting the first direction; a first backside separation structure penetrating the substrate below the gate electrode in a third direction intersecting the first direction and the second direction; and a second backside separation structure penetrating the substrate and overlapping the upper separation structure in the third direction.

A semiconductor device includes a substrate, and a first transistor including a first channel semiconductor layer provided on the substrate, a pair of first source and drain semiconductor layers provided on the substrate and sandwiching the first channel semiconductor layer, a first gate electrode disposed between the pair of first source and drain semiconductor layers, the first gate electrode and the first channel semiconductor layer sandwiching a first gate insulating film, a second channel semiconductor layer provided over and spaced apart from the first channel semiconductor layer, a pair of second source and drain semiconductor layers provided over the pair of first source and drain semiconductor layers and sandwiching the second channel semiconductor layer, and a second gate electrode disposed between the pair of second source and drain semiconductor layers, the second gate electrode and the second channel semiconductor layer sandwiching a second gate insulating film.

Semiconductor devices having nanosheet architectures, e.g., transistors such as horizontal gate-all-around (hGAA) structures, methods, and apparatuses for forming such semiconductor devices are described. The methods comprise forming a cladding material around each of a first plurality of nanosheets; oxidizing a portion of the cladding material to form an oxidize film, such as a silicon oxide (SiO.sub.2) film, around the cladding material and a form a second plurality of nanosheets; annealing the second plurality of nanosheets at a temperature of less than or equal to 850 C.; and removing the oxide film.

An exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interfacial layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). The gate stack wraps and/or surrounds a first semiconductor layer disposed over a second semiconductor layer. The gate dielectric and the work function layer (and not the cap and/or the bulk fill layer) fill a space between the first semiconductor layer and the second semiconductor layer. A ratio of oxygen in outer portions of the gate stack to inner portions of the gate stack may be about 1 to about 1.25. A thickness of the work function layer at inner portions of the gate stack may be less than a thickness of the work function layer at outer portions of the gate stack.

A semiconductor device includes: a substrate including active patterns; a device isolation layer disposed between the active patterns; a stacked pattern disposed on the substrate; a power transmission network layer disposed on a first surface of the substrate; a first through via penetrating the stacked pattern; and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the device isolation layer.

A method for forming a semiconductor structure is provided. The method includes forming a first active region in which first semiconductor layers and second semiconductor layers are alternatingly stacked over a first lower fin element. In a plan view, the active region includes a first portion and a second portion narrower than the first portion. The method also includes removing the first semiconductor layers of the first active region. The second semiconductor layers of the first portion of the first active region form first nanostructures, and the second semiconductor layers of the second portion of the first active region form second nanostructures. The method also includes forming a first gate stack to surround the first nanostructures, and forming a second gate stack to surround the second nanostructures.

One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.

Provided is a semiconductor device including a substrate, a lower power line disposed under the substrate, a source/drain pattern on the substrate, a channel pattern, on side surfaces of the source/drain pattern, including a plurality of semiconductor patterns stacked on each other, a gate electrode between the plurality of semiconductor patterns, a backside active contact penetrating the substrate to electrically connect the lower power line and the source/drain pattern, and a backside isolation structure penetrating the substrate and the backside active contact, and disposed under the gate electrode. An uppermost surface of the backside active contact is located at a higher level than an uppermost surface of the backside isolation structure.

A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.