A semiconductor device may include a lower active pattern extending in a first direction and comprising a lower channel pattern, an upper active pattern spaced apart from the lower active pattern in a second direction, the second direction intersecting the first direction, and the upper active pattern extending in the first direction, wherein the upper active pattern comprises an upper channel pattern, a gate electrode surrounding the lower channel pattern and the upper channel pattern, and the gate electrode extending in a third direction, the third direction intersecting each of the first and second directions, a lower source/drain pattern on at least one side of the lower channel pattern, an upper source/drain pattern on at least one side of the upper channel pattern, and an upper source/drain contact penetrating through the upper source/drain pattern in the second direction.

Provided is a semiconductor device including: a lower active region extending in a first direction and including a lower channel pattern and a lower source/drain pattern on a side of the lower channel pattern; an upper active region spaced apart from the lower channel pattern in a second direction, extending in the first direction, and including an upper channel pattern and an upper source/drain pattern on a side of the upper channel pattern; a gate electrode surrounding the upper and lower channel patterns, and extending in a third direction; a lower source/drain contact below and connected to the lower source/drain pattern; an upper source/drain contact above and connected to the upper source/drain pattern; a vertical via on one side of the upper source/drain pattern and connected to the lower and upper source/drain contacts; and a first dummy structure on another side of the upper source/drain pattern, the first dummy structure including a first dummy pattern extending in the first direction.

The disclosed technology relates to dynamic random access memory (DRAM) devices. The disclosed technology provides an integrated DRAM device including a DRAM and a logic circuit configured to control the DRAM. In one aspect, a DRAM device includes a plurality of stacked transistors arranged in a first region of the DRAM device, the stacked transistors being disposed one over another along a stacking direction, and a storage capacitor arranged in a second region of the DRAM device. The first region is positioned above the second region along the stacking direction. One of the plurality of stacked transistors is connected to the storage capacitor to form a DRAM cell of the DRAM, and remaining one or ones of the plurality of stacked transistors forms at least a portion of the logic circuit.

A CFET transistor device, including: a substrate; a first semiconductor nanosheet and a second semiconductor nanosheet; an insulating layer arranged between the first and second nanosheets; a first gate arranged around a first part of the first nanosheet, and a second gate arranged around a first part of the second nanosheet; first inner spacers arranged against second parts of the first nanosheet, between which the first part of the first nanosheet is arranged, and second inner spacers arranged against second parts of the second nanosheet between which the first part is arranged; and wherein the first and second inner spacers respectively include first and second low-permittivity dielectric materials different from each other.

A semiconductor device including a stacked multi-gate transistor includes a substrate, a first active pattern including a first lower active pattern and a first upper active pattern, a second active pattern including a second lower active pattern and a second upper active pattern, a first gate structure, a second gate structure on the second active pattern, the first gate structure and the second gate structure are aligned, a cutting structure between the first active pattern and the second active pattern, the cutting structure separating the first gate structure and the second gate structure, a front wiring pattern that extends on an upper surface of the cutting structure, a first back wiring pattern, and a first through-via that extends into the substrate and the cutting structure, the first through-via electrically connects the front wiring pattern and the first back wiring pattern.

A semiconductor device includes: a first active pattern; a first source/drain pattern disposed on the first active pattern; a second active pattern spaced apart from the first active pattern in a first direction; a second source/drain pattern disposed on the second active pattern; a gate electrode overlapping the first active pattern and extending in a second direction intersecting the first direction; and a dummy structure disposed between the first active pattern and the second active pattern and between the first source/drain pattern and the second source/drain pattern, wherein the dummy structure includes: a first line portion extending in the second direction; a second line portion extending in the second direction and spaced apart from the first line portion in the first direction; and a first connection portion connecting the first line portion and the second line portion to each other.

A dopant may included in one or more sacrificial layers, e.g., silicon layers or silicon germanium layers, used for forming nanoribbon transistors. Adding a dopant to a silicon germanium layer may cause the silicon germanium to be more stress neutral, to prevent relaxation after etching stacks of individuated nanoribbons. Alternatively, when added to one or more sacrificial layers of silicon, the doped silicon layers may counteract elastic stress from the silicon germanium layers. The dopant layers may be included at various positions in a stack of materials. The dopant layer may include one or more dopants selected from carbon, arsenic, boron, and phosphorus.

Embodiments described herein generally relate to methods of forming hardmask and bottom dielectric isolation layers in vertical trench structures. A method of forming a gate-all-around field-effect transistor includes depositing a conformal oxide layer on a channel surface and a bottom surface of vertical structures of a substrate, the vertical structures including an NMOS portion having NMOS vertical structures defining NMOS contact trenches and a PMOS portion having PMOS structures defining PMOS contact trenches having a PMOS source/drain layer deposited therein. The method further includes selectively etching the conformal oxide layer at the bottom surface of the vertical structures, inhibiting the conformal oxide layer, selectively depositing a nitride layer at the bottom surface of the vertical structures, etching the conformal oxide layer to expose the channel surface of the vertical structures, and depositing an NMOS source/drain layer on the bottom surface of the NMOS contact trenches.

A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.

A method of manufacturing a semiconductor device comprising: forming active structures; forming preliminary gate dielectric layers on the active structures; forming a first dipole layer including a first dipole material and a second dipole layer including a second dipole material on the preliminary gate dielectric layers; removing the first and second dipole layers in regions other than a first region of the active structures; removing a portion of the second dipole layer in regions other than a second region of the active structures, wherein each of the first and second regions includes at least two active structures, and the first region and the second region overlap to form an overlapping region; and performing a heat treatment process of diffusing the first and second dipole materials into the preliminary gate dielectric layers, wherein the overlapping region includes at least one of the active structures.