Provided is a semiconductor device including an MOS gate structure, comprising: an underlying layer provided on a front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer dielectric film provided above the underlying layer; a contact hole provided in the interlayer dielectric film and reaching the underlying layer from an upper surface of the interlayer dielectric film; a first alloy layer provided on a bottom portion of the contact hole; and a second alloy layer provided on a side wall of the contact hole. Provided is a manufacturing method of a semiconductor device including: depositing an initial polycrystalline film and a first initial metal film on an inner wall of the contact hole; and forming a first alloy layer on a bottom portion of the contact hole and forming a second alloy layer on a side wall of the contact hole, by heating the semiconductor substrate.

A semiconductor device and power conversion device are provided in which the p-body layer area of a diode portion of an RC-IGBT is reduced, hole injection is suppressed, and the recovery characteristic is improved. The semiconductor device has first and second body layers and first trenches provided therebetween. First and second gate electrodes are formed on side walls on the first and second body layer sides, respectively, with a gate insulation film between the gate electrodes and body layer sides. The first and second gate electrodes are separated by a first insulation film. The diode has third and fourth body layers of a first conductivity type, and a second trench provided therebetween. The second trench has first and second electrodes formed on side walls on the third and fourth body layer sides, respectively, with insulation films therebetween and the first and second electrodes are separated by a second insulation film.

A semiconductor device including a transistor portion and a diode portion, including a plurality of trench portions provided at a front surface of a semiconductor substrate, a drift region of a first conductivity type provided in the semiconductor substrate, a base region of a second conductivity type provided above the drift region, an emitter region of the first conductivity type provided above the base region and having a doping concentration higher than that of the drift region, a contact region of the second conductivity type provided above the base region with a doping concentration higher than the base region, an injection suppression region provided at the front surface of the semiconductor substrate, and an emitter electrode provided above the semiconductor substrate, in which the transistor portion has a main region for performing transistor operation, and the injection suppression region is provided in the main region of the transistor portion.

A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

Provided are a semiconductor device, a method for manufacturing the semiconductor device, and a power conversion device for allowing the low injection of the diode unit by forming the Schottky barrier diode in the diode unit of the RC-IGBT through a process simpler than the usual process. A semiconductor device (RC-IGBT) is formed as an RC-IGBT having an IGBT unit and a diode unit formed in a single chip. The diode unit includes a plurality of first trenches connected to a gate potential or an emitter potential in the absence of a body layer of second conductive type, and a second trench which is formed between two of the first trenches, and connected to the emitter potential. A Schottky barrier diode is provided, which is constituted by the second trench and a drift layer of a first conductive type in contact with a side wall of the second trench.

A semiconductor device is provided, which includes a boundary member between an auxiliary element and a main surface of a semiconductor substrate to reduce the step of a protective film covering the auxiliary element. A semiconductor device is provided, comprising a semiconductor substrate having a first main surface having a first region, a second region, and a third region located between the first region and the second region in plan view, a transistor formed in the first region, an auxiliary element formed in the second region, a boundary member formed in the third region, and a protective film covering the auxiliary element and the boundary member. The height from the first main surface to the upper surface of the boundary member is lower than the height from the first main surface to the upper surface of the auxiliary element.

An object is to provide a semiconductor device whose flexibility of assembly can be increased. A semiconductor device includes a semiconductor substrate having a rectangular active region in a top view, and a termination region around the active region, and includes: a gate electrode on an upper surface of the semiconductor substrate in the active region; and a gate line formed above the upper surface of the semiconductor substrate in the termination region and being electrically connected to the gate electrode, wherein the gate line is rectangular in a top view, and surrounds the active region, the gate line includes a gate pad portion for connecting the gate electrode to an external portion through bonding, and the gate pad portion is disposed on an entirety of at least one side of the gate line.

A semiconductor device includes: a first-1 trench gate structure, a first-2 trench gate structure, and a barrier structure provided in a first trench; a second trench gate structure provided in a second trench; and a third trench gate structure provided in a third trench and connected to the first-2 trench gate structure and the second trench gate structure. The barrier structure includes an insulating film provided at least partially between the first-1 upper electrode and the first-2 upper electrode and insulating the first-1 upper electrode and the first-2 upper electrode.

Provided is a semiconductor device including: a drift region of a first conductivity type which is provided in a semiconductor substrate; an emitter region of the first conductivity type which is provided at a front surface of the semiconductor substrate, and which has a doping concentration higher than that of the drift region; a plurality of trench portions which are provided above the drift region; a trench contact portion which is provided in a mesa portion between the plurality of trench portions; and a plug region of a second conductivity type which is provided in contact with a lower end of the trench contact portion. The trench contact portion may have a main trench contact which extends in a trench extension direction in a top view, and a sub-trench contact which extends from the main trench contact in a direction different from the trench extension direction in the top view.

Provided is a semiconductor device including: an active portion; and a temperature sensitive portion, in which the temperature sensitive portion includes a temperature sensitive trench portion which is provided on a front surface side of a semiconductor substrate, a temperature sensitive anode region which is provided inside a trench of the temperature sensitive trench portion, and a temperature sensitive cathode region which is provided in contact with the temperature sensitive anode region inside the trench of the temperature sensitive trench portion.