Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

A semiconductor device includes a first fin pattern extending in a first direction, source/drain patterns on the first fin pattern, a gate electrode extending in a second direction, an insulating structure in contact with the first fin pattern, a lower conductive pattern and an upper conductive pattern overlapping the insulating structure in a third direction, and a connection contact extending through the insulating structure and electrically connecting the lower conductive pattern and the upper conductive pattern. The first fin pattern includes a first fin portion, a second fin portion spaced apart from the first fin portion, and a third fin portion between the first fin portion and the second fin portion. A width in the second direction of the first fin portion and a width in the second direction of the second fin portion are greater than a width in the second direction of the third fin portion.

A semiconductor device may include a channel pattern on a substrate, a source/drain pattern electrically connected to the channel pattern, a gate electrode on the channel pattern, an interlayer insulating layer on the source/drain pattern, and an active contact that extends into the interlayer insulating layer and is electrically connected to the source/drain pattern. The active contact may include a lower active contact, which includes a barrier pattern and a lower metal pattern on the barrier pattern, and an upper active contact on the lower active contact. The upper active contact may include an upper metal pattern and an insulating pattern on side surfaces of the upper metal pattern. The lower metal pattern and the upper metal pattern may be in contact with each other.

Provided is a semiconductor device including a first active pattern and a second active pattern on a substrate, a first source/drain pattern and a first channel pattern on the first active pattern, a second source/drain pattern and a second channel pattern on the second active pattern, and a gate electrode crossing each of the first channel pattern and the second channel pattern. Along a horizontal extension direction of the gate electrode, a first width of an upper surface of the first channel pattern is greater than a second width of an upper surface of the second channel pattern, and an upper surface of the first source/drain pattern is located at a vertically higher level than the upper surface of the first channel pattern.

An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.

A semiconductor device may include a first fin pattern, a first source/drain pattern on the first fin pattern, a second fin pattern spaced apart in a first direction from the first fin pattern, a second source/drain pattern on the second fin pattern, a first gate electrode overlapping the first fin pattern and extending in a second direction crossing the first direction, a second gate electrode overlapping the second fin pattern and extending in the second direction, and a first dummy structure between the first fin pattern and the second fin pattern and between the first gate electrode and the second gate electrode. The first dummy structure may include first to third line parts extending in the second direction, first and second connection parts connecting the first and second line parts to each other, and a third connection part connecting the second and third line parts to each other.

A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.

A semiconductor device may include a substrate, a first source/drain pattern and a second source/drain pattern spaced apart in a first direction on the substrate, a height from an upper surface of a central portion of the first source/drain pattern to an upper surface of the substrate in a vertical direction is lower than a height from an upper surface of an edge of the first source/drain pattern to the upper surface of the substrate, a plurality of channel patterns connecting between the first source/drain pattern and the second source/drain pattern, and the plurality of channel patterns stacked to be spaced apart from each other, a gate structure surrounding the plurality of channel patterns and extending in a second direction, and a contact plug extending in the vertical direction from an upper surface of the first source/drain pattern, and the contact plug connected to the first source/drain pattern.

The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

A semiconductor device includes a gate structure; a first source/drain region and a second source/drain region; a plurality of channel layers, wherein the plurality of channel layers includes a lowermost channel layer, an uppermost channel layer, and a first intermediate channel layer; and a contact plug, wherein each of the first source/drain region and the second source/drain region includes a plurality of protrusions including an uppermost protrusion, a lowermost protrusion, and a first intermediate protrusion, and wherein a distance between the uppermost protrusion of the first source/drain region and the uppermost protrusion of the second source/drain region and a distance between the lowermost protrusion of the first source/drain region and a lowermost protrusion of the second source/drain region are each less than a distance between the first intermediate protrusion of the first source/drain region and the first intermediate protrusion of the second source/drain region.