A semiconductor device may include a substrate, a first source/drain pattern and a second source/drain pattern spaced apart in a first direction on the substrate, a height from an upper surface of a central portion of the first source/drain pattern to an upper surface of the substrate in a vertical direction is lower than a height from an upper surface of an edge of the first source/drain pattern to the upper surface of the substrate, a plurality of channel patterns connecting between the first source/drain pattern and the second source/drain pattern, and the plurality of channel patterns stacked to be spaced apart from each other, a gate structure surrounding the plurality of channel patterns and extending in a second direction, and a contact plug extending in the vertical direction from an upper surface of the first source/drain pattern, and the contact plug connected to the first source/drain pattern.

The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

A display panel includes a gate electrode, a source electrode, a drain electrode, and a metal oxide layer disposed corresponding to the gate electrode. The metal oxide layer includes a lower metal oxide layer and an upper metal oxide layer stacked on the lower metal oxide layer. The lower metal oxide layer includes an indium oxide and a lanthanoid oxide. The upper metal oxide layer is located on a surface of the lower metal oxide layer adjacent to the source electrode and the drain electrode. The source electrode and the drain electrode are connected to the upper metal oxide layer. The upper metal oxide layer includes an indium oxide and a lanthanoid oxide, and the upper metal oxide layer includes polycrystalline phase.

A semiconductor device includes a power transmission network layer on a first surface of a substrate, a source/drain pattern on the substrate, the source/drain pattern including a first pattern including a first material and a second pattern including a second material that is different from the first material, and a backside conductive contact that extends into the substrate and into the source/drain pattern. The backside conductive contact includes a first region that extends into the first pattern of the source/drain pattern and a second region on the first region. The second region of the backside conductive contact has a second width that is greater than a first width of the first region of the backside conductive contact in a direction parallel to a second surface of the substrate.

A semiconductor device is provided. The semiconductor device includes: a first active pattern on a first active region of a substrate; a second active pattern on a second active region of the substrate, wherein the first active region is spaced apart from the second active region in a first direction; a first channel pattern that includes first semiconductor patterns that are spaced apart from each other and vertically stacked on the first active pattern; and a gate electrode on the first channel pattern. The gate electrode includes: first metal patterns on the first semiconductor patterns on the first active region; and a gap-fill pattern between the first metal patterns on the first active region. A maximum width in the first direction of the gap-fill pattern is less than a maximum width in the first direction of the first metal patterns.

A semiconductor device includes a gate structure; a first source/drain region and a second source/drain region; a plurality of channel layers, wherein the plurality of channel layers includes a lowermost channel layer, an uppermost channel layer, and a first intermediate channel layer; and a contact plug, wherein each of the first source/drain region and the second source/drain region includes a plurality of protrusions including an uppermost protrusion, a lowermost protrusion, and a first intermediate protrusion, and wherein a distance between the uppermost protrusion of the first source/drain region and the uppermost protrusion of the second source/drain region and a distance between the lowermost protrusion of the first source/drain region and a lowermost protrusion of the second source/drain region are each less than a distance between the first intermediate protrusion of the first source/drain region and the first intermediate protrusion of the second source/drain region.

Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and a first channel layer and a second channel layer. The semiconductor structure further includes an isolation structure over the substrate and a first gate structure over the first channel layer and the isolation structure. The semiconductor structure further includes a second gate structure over the second channel layer and the isolation structure and an isolation feature laterally sandwiched between the first gate structure and the second gate structure and extending over the isolation structure. In addition, the isolation feature has a top width and a bottom width that is greater than the top width, and an interface between the isolation feature and the first gate structure includes a curved profile.