Provided is a semiconductor device which includes: a 1.sup.st source/drain pattern for a 1.sup.st transistor; a 2.sup.nd source/drain pattern for a 2.sup.nd transistor, above the 1.sup.st source/drain pattern, the 2.sup.nd source/drain pattern having a smaller width than the 1.sup.st source/drain pattern in a channel-width direction; a 1.sup.st isolation layer surrounding the 1.sup.st source/drain pattern; a 2.sup.nd isolation layer surrounding the 2.sup.nd source/drain pattern, the 1.sup.st and 2.sup.nd isolation layers including a first material; a liner surrounding the 1.sup.st source/drain pattern, the liner including a 2.sup.nd material; and a contact structure on the 1.sup.st source/drain pattern, wherein the contact structure penetrates the 2.sup.nd isolation layer and the liner to contact the 1.sup.st source/drain pattern without penetrating the 1.sup.st isolation layer.

Provided is a semiconductor device which includes: a substrate; a channel structure on the substrate; a source/drain pattern connected to the channel structure; a gate structure on the channel structure; an inner spacer structure comprising an inner spacer between the source/drain pattern and the gate structure, and an inner spacer residue connected to the inner spacer structure; and an inner isolation structure between the inner spacer residue and a bottom surface of the source/drain pattern.

A semiconductor device includes insulating isolation patterns each including a void, semiconductor patterns respectively stacked on the insulating isolation patterns, gate structures respectively extending around the semiconductor patterns, first and second source/drain patterns respectively connected to opposing sides of the plurality of semiconductor patterns in a first direction, an active contact structure extending between insulating isolation patterns adjacent to the first source/drain pattern and connected to the first source/drain pattern, a dummy contact structure extending between the insulating isolation patterns adjacent to the second source/drain pattern and electrically isolated from the second source/drain pattern, and an interconnection line on lower surfaces of the insulating isolation patterns, electrically connected to the active contact structure, and electrically isolated from the dummy contact structure.

A semiconductor device includes: a lower transistor including a lower channel structure and a lower source/drain structure on the lower channel structure; and an upper transistor above the lower transistor, the upper transistor including an upper channel structure and an upper source/drain structure on the upper channel structure, wherein a portion of the upper channel structure overlaps the lower channel structure in a vertical direction, and another portion of the upper channel structure does not overlap the lower channel structure in the vertical direction.

A semiconductor device includes a first active pattern including first sheets spaced apart in a first direction perpendicular to a surface of a substrate, a second active pattern on the first active pattern and including second sheets spaced apart in the first direction, a first source/drain pattern connected to the first active pattern in a second direction, a second source/drain pattern on the first source/drain pattern and connected to the second active pattern in the second direction, and a gate electrode extending in a third direction and extending around the first and the second active patterns. The first source/drain pattern includes a first film along an inner surface of a recess where the first source/drain pattern is disposed and a second film on the first film and filling the recess. On a cross-section including the first and third directions, the recess decreases in width with decreasing distance to the substrate.

A semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a plurality of lower nanosheets stacked on the active pattern and spaced apart from each other in a vertical direction, a nanosheet isolation layer including an insulating material on an upper surface of an uppermost nanosheet of the plurality of lower nanosheets, a plurality of upper nanosheets stacked on an upper surface of the nanosheet isolation layer and spaced apart from each other in the vertical direction, a gate electrode extending in a second direction different from the first direction on the active pattern, the gate electrode extending on the plurality of lower nanosheets, the nanosheet isolation layer, and the plurality of upper nanosheets, and an inner spacer on opposing sidewalls of the gate electrode between either adjacent ones of the upper nanosheets, or adjacent ones of the lower nanosheets.

A semiconductor device may include a first active pattern on a substrate, channel patterns on the first active pattern, a gate electrode extending in a first direction on the first active pattern, and a backbone structure extending in a second direction intersecting the first direction. The first active pattern includes a first region and a second region spaced apart in the second direction, the first active pattern includes a first active sidewall in direct contact with the backbone structure and a second active sidewall spaced apart from the first active sidewall in the first direction, and a distance between the first active sidewall and the second active sidewall in the first direction varies as the first active pattern extends from the first region toward the second region.

A semiconductor device includes a first fin pattern extending in a first direction, source/drain patterns on the first fin pattern, a gate electrode extending in a second direction, an insulating structure in contact with the first fin pattern, a lower conductive pattern and an upper conductive pattern overlapping the insulating structure in a third direction, and a connection contact extending through the insulating structure and electrically connecting the lower conductive pattern and the upper conductive pattern. The first fin pattern includes a first fin portion, a second fin portion spaced apart from the first fin portion, and a third fin portion between the first fin portion and the second fin portion. A width in the second direction of the first fin portion and a width in the second direction of the second fin portion are greater than a width in the second direction of the third fin portion.

A semiconductor device includes a substrate, a transistor stack on the substrate, a first source/drain structure on a first side of the transistor stack, and a second source/drain structure on a second side of the transistor stack, where the transistor stack includes a lower transistor on the substrate, the lower transistor including a lower channel layer and a lower gate structure surrounding the lower channel layer, an upper transistor on the lower transistor, the upper transistor including an upper channel layer and an upper gate structure surrounding the upper channel layer, and a first connecting layer between the lower gate structure and the upper gate structure, and the first source/drain structure and the second source/drain structure are connected via the first connecting layer.

A method includes forming a stack of channel layers and sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, and recessing a portion of the fin-shape structure to form a recess. A top surface of the substrate under the recess is covered at least by a bottommost sacrificial layer of the stack. The method also includes forming inner spacers on terminal ends of the sacrificial layers that are above the bottommost sacrificial layer, depositing an undoped layer in the recess, and forming a doped epitaxial feature over the undoped layer. The undoped layer covers terminal ends of a bottommost channel layer of the stack. The doped epitaxial feature covers terminal ends of the channel layers that are above the bottommost channel layer.