Provided is a semiconductor device which includes: an isolation structure; a 1.sup.st contact structure in the isolation structure; and a 2.sup.nd contact structure adjacent to and at a lateral side of the 1.sup.st contact structure, in the isolation structure, wherein at least one of the 1.sup.st contact structure and the 2.sup.nd contact structure has an extra isolation layer on a side surface thereof facing the other of the 1.sup.st contact structure and the 2.sup.nd contact structure.

A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.

Semiconductor devices and manufacture methods thereof are provided. In one aspect, a semiconductor device includes a first transistor, where the first transistor includes first channel patterns stacked on a first active pattern with a first channel length and first source and drain patterns; and a second transistor, where the second transistor includes second channel patterns stacked on a second active pattern with a second channel length greater than the first channel length and second source and drain patterns. Each of the first source and drain patterns include a first high-resistivity bottom epitaxial layer, a first epitaxial layer, and a second epitaxial layer. Each of the second source and drain patterns includes a third epitaxial layer on the second active pattern and a fourth epitaxial layer. A bottom level of the first source and drain patterns is lower than a bottom level of the second source and drain patterns.

A semiconductor device may include a substrate, a first source/drain pattern and a second source/drain pattern spaced apart in a first direction on the substrate, a height from an upper surface of a central portion of the first source/drain pattern to an upper surface of the substrate in a vertical direction is lower than a height from an upper surface of an edge of the first source/drain pattern to the upper surface of the substrate, a plurality of channel patterns connecting between the first source/drain pattern and the second source/drain pattern, and the plurality of channel patterns stacked to be spaced apart from each other, a gate structure surrounding the plurality of channel patterns and extending in a second direction, and a contact plug extending in the vertical direction from an upper surface of the first source/drain pattern, and the contact plug connected to the first source/drain pattern.

An integrated circuit device includes cell transistors at a first vertical level, a front wiring structure at a second vertical level higher than the first vertical level, and a rear wiring structure at a third vertical level lower than the first vertical level. The rear wiring structure includes a device isolation layer arranged on bottom surfaces of the cell transistors, rear contacts arranged in rear contact holes passing through the device isolation layer, a buried interconnector arranged in a recess region that extends into the device isolation layer, connected to a first and second rear contacts, among the rear contacts, and extending in a first horizontal direction or a second horizontal direction, a buried insulating layer arranged in the recess region and arranged on a bottom surface of the buried interconnector, and a rear wiring layer on bottom surfaces of the device isolation layer and the buried insulating layer.

Semiconductor devices include stacked nanosheet channels with inner spacers between respective pairs of the stacked nanosheet channels. Dummy nanosheet remnants are below respective inner spacers, vertically aligned with the respective inner spacers. A source/drain structure is on sidewalls of the plurality of stacked nanosheet channels. A backside contact makes contact with the source/drain structure.

Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.

Provided is a semiconductor device including a lower source/drain pattern, a lower channel structure connected to the lower source/drain pattern, a lower gate electrode overlapping the lower channel structure and extending in a first direction, a lower active contact on the lower source/drain pattern, an upper channel structure overlapping the lower channel structure, an upper source/drain pattern connected to the upper channel structure, an upper gate electrode overlapping the upper channel structure and extending in the first direction, an interlayer structure between the lower channel structure and the upper channel structure, and a through active contact extending through the interlayer structure, and electrically connected to the upper source/drain pattern and the lower active contact.

A semiconductor device includes a substrate having first and second regions; first and second channel layers on the first region and the second region with a first gate electrode and a second gate electrode thereon, respectively; a first source/drain region and a second source/drain region on at least one side of the first gate electrode and the second gate electrode, respectively; an auxiliary epitaxial pattern extending into the second source/drain region from an upper surface thereof, a first contact plug extending into the first source/drain region from an upper surface thereof; and a second contact plug extending into the auxiliary epitaxial pattern from an upper surface thereof. The first source/drain region has a first depth and a first impurity region including first impurities, the second source/drain region has a second depth and a second impurity region including second impurities, with the second depth greater than the first depth.

A method of forming an integrated circuit device includes providing a stacked transistor structure on a substrate. The stacked transistor structure includes a first channel pattern of a first transistor and a second channel pattern of a second transistor stacked on the first channel pattern. Second source/drain regions of the second transistor are formed at opposing ends of the second channel pattern, and an oxidation process is performed to oxidize upper and lower surfaces of the second source/drain regions and side surfaces of the first channel. First source/drain regions of the first transistor are then formed at opposing ends of the first channel pattern. Related devices and fabrication methods are also discussed.