An integrated circuit device includes an active region extending lengthwise in a first direction on a substrate, a gate structure including a gate line, a high dielectric layer, and an interface dielectric layer, which extend lengthwise in a second direction perpendicular to the first horizontal direction on the active region, a nanosheet arranged on a fin upper surface of the active region and contacting the gate structure, a source/drain region arranged on the active region and contacting the nanosheet, and under the source/drain region in a direction perpendicular to both the first direction and the second direction, a lower insulating spacer arranged in a source/drain recess extending from the fin upper surface of the active region, wherein the interface dielectric layer includes a first portion extending on the nanosheet, and a second portion extending on the source/drain region, and wherein a first thickness of the first portion is different from a second thickness of the second portion.

An integrated circuit device includes a substrate having an active region defined by a device isolation film, a recess trench disposed in the active region, spaced apart from the device isolation film, and extending in a vertical direction from a main surface of the substrate towards an interior of the substrate, and a recess channel transistor including a gate electrode disposed within the recess trench, the recess channel transistor including a channel positioned along a surface of the recess trench, wherein each of the recess trench and the gate electrode has a closed-loop shape in a plan view.

Provided is a stacked semiconductor device which includes: a substrate; a 1.sup.st source/drain region on the substrate; and a 2.sup.nd source/drain region vertically above the 1.sup.st source/drain region, the 2.sup.nd source/drain region vertically overlapping a 1.sup.st portion, among the 1.sup.st portion and a 2.sup.nd portion, of the 1.sup.st source/drain region, wherein a 1.sup.st portion of a top surface of the substrate vertically below the 1.sup.st portion of the 1.sup.st source/drain region and a 2.sup.nd portion of the top surface of the substrate vertically below the 2.sup.nd portion of the 1.sup.st source/drain region are coplanar or aligned.

A semiconductor device includes an active pattern spaced apart in a first direction, and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern located on the active pattern and alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern extending in the first direction and located on the lower channel pattern and the upper channel pattern; a separation pattern located between one of the lower source/drain pattern and the upper source/drain pattern and another of the lower source/drain pattern and the upper source/drain pattern in the second direction; and a gate cutting pattern extending in the second direction across the gate pattern to separate the gate pattern.

A semiconductor device includes a substrate, a first channel pattern on the substrate, the first channel pattern having a first width, a first gate electrode extending in a second direction, a first gate capping pattern on an upper surface of the first gate electrode, a second channel pattern spaced apart from the first channel pattern, the first channel pattern having a second width, a second gate electrode extending in the second direction on the second channel pattern, a second gate capping pattern on an upper surface of the second gate electrode, a source/drain pattern on at least one side of the second channel pattern, a first source/drain contact connected to the source/drain pattern, a second source/drain contact spaced apart from the first source/drain contact, and a contact isolation film between the first source/drain contact and the second source/drain contact. The second width is greater than the first width.

Embodiments of the present disclosure provide a semiconductor device structure and methods for forming the same. The structure includes a first semiconductor layer disposed in a first region, a second semiconductor layer disposed over the first semiconductor layer in the first region, a first gate electrode layer disposed between the first and second semiconductor layers in the first region, a first dielectric spacer disposed adjacent the first gate electrode layer in the first region, a third semiconductor layer disposed in a second region, a fourth semiconductor layer disposed over the third semiconductor layer in the second region, a second gate electrode layer disposed between the third and fourth semiconductor layers in the second region, and a second dielectric spacer disposed adjacent the second gate electrode layer in the second region. The second dielectric spacer has a thickness smaller than a first thickness of the first dielectric spacer.

An integrated circuit device includes a gate line, a source/drain region adjacent to the gate line in a first direction, a backside via contact connected to the source/drain region, a backside power rail integrally connected to the backside via contact and spaced apart from the source/drain region in a second direction with the backside via contact therebetween, and a backside insulating pattern overlapping the gate line in the second direction and contacting a sidewall of the backside power rail in the first direction, wherein the backside insulating pattern includes a first backside insulating portion having a gradually increasing width in the first direction with an increasing distance from the gate line, and a second backside insulating portion integrally connected to the first backside insulating portion and having a gradually decreasing width in the first direction with an increasing distance from the gate line.

A semiconductor device includes a substrate, a source/drain region on the substrate, a channel structure on the substrate and electrically connected to the source/drain region, a gate structure on the substrate and at least partially surrounding the channel structure, and a stressor layer in contact with an upper surface of the source/drain region and configured to apply compressive stress or tensile stress to the source/drain region.

A semiconductor device includes a substrate; an active region on the substrate and extending in a first direction; a device isolation film around the active region in the substrate; a first gate electrode extending on the active region in a second direction that intersects the first direction; a second gate electrode extending on the active region in the second direction and spaced apart from the first gate electrode in the first direction; a first connection gate electrode extending in the first direction and connected to a first end of the first gate electrode and a first end of the second gate electrode; and a source/drain region in the active region at a side of the first gate electrode.

Provided is a semiconductor device which includes: a 1.sup.st source/drain region; a 2.sup.nd source/drain region above the 1.sup.st source/drain region; a side via structure connected to the 2.sup.nd source/drain region; a 1.sup.st backside contact plug on the 1.sup.st source/drain region; a 2.sup.nd backside contact plug on the side via structure; a 1st backside metal line on the 1.sup.st backside contact plug; a 2.sup.nd backside metal line on the 2.sup.nd backside contact plug; and a 1.sup.st deep trench isolation structure on a side surface of the 2.sup.nd backside contact plug.