Provided is a semiconductor device including a base pattern, channel layers disposed to be spaced apart from each other in a first direction perpendicular to a frontside of the base pattern on the frontside of the base pattern, a first source/drain area and a second source/drain area electrically connected to the channel layers on the frontside of the base pattern, a backside contact plug electrically connected to the first source/drain area from a backside of the base pattern, and a frontside contact plug electrically connected to the second source/drain area above the frontside of the base pattern, and the first source/drain area includes a first-first layer disposed on side surfaces of the channel layers of which each is perpendicular to a second direction crossing the first direction, and a first-second layer disposed on the first-first layer, and the backside contact plug is spaced apart from the first-first layer.

Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and a first channel layer and a second channel layer. The semiconductor structure further includes an isolation structure over the substrate and a first gate structure over the first channel layer and the isolation structure. The semiconductor structure further includes a second gate structure over the second channel layer and the isolation structure and an isolation feature laterally sandwiched between the first gate structure and the second gate structure and extending over the isolation structure. In addition, the isolation feature has a top width and a bottom width that is greater than the top width, and an interface between the isolation feature and the first gate structure includes a curved profile.

Provided is an integrated circuit device including: first and second transistors including first and second channel regions and first and second source/drain regions respectively connected to the first and second channel regions; and first and second contact structures respectively connected to the first and second source/drain regions; wherein each of the first and second contact structures includes at least two metal-containing films, wherein the first contact structure includes a first major metal plug having a largest volume among volumes of the at least two metal-containing films of the first contact structure, wherein the second contact structure includes a second major metal plug having a largest volume among volumes of the at least two metal-containing films of the second contact structure, wherein the first and second major metal plugs respectively include different metals, and wherein the first and second major metal plugs have different cross-sectional shapes.

Provided is a semiconductor device including a base pattern; channel patterns on an upper surface of the base pattern; a gate structure on the upper surface of the base pattern; a first source/drain pattern on a first side of the gate structure; a second source/drain pattern on a second side of the gate structure; a first source/drain liner between the first source/drain pattern and the gate structure; a second source/drain liner between the second source/drain pattern and the gate structure; and a backside plug in the base pattern, wherein the backside plug is electrically connected to the first source/drain pattern, wherein an upper end of the first source/drain liner is between the first source/drain pattern and the gate structure, and wherein a lower end of the first source/drain liner is between the upper surface of the base pattern and a lower surface of the base pattern.

An integrated circuit device may include a substrate and a cell structure on an upper surface of the substrate. The cell structure may comprise at least a portion of a first transistor that comprises a first sidewall and a second sidewall that is opposite to the first sidewall and at least a portion of a second transistor that comprises a third sidewall and a fourth sidewall that is opposite to the third sidewall between the upper surface of the substrate and the first transistor. One of the third sidewall and the fourth sidewall may overlap the first transistor. The at least the portion of the first transistor may have a first cell width. The at least the portion of the second transistor may have a second cell width. The first cell width may be different from the second cell width.

A semiconductor device includes a back interlayer insulating film; a plurality of first channel patterns on the back interlayer insulating film and spaced apart from each other in a vertical direction; a plurality of second channel patterns on the back interlayer insulating film and spaced apart from each other in the vertical direction; a source/drain pattern between the first channel patterns and the second channel patterns; and a source/drain contact connected to the source/drain pattern, wherein the source/drain pattern includes a first layer which comes into contact with the first channel patterns and the second channel patterns, a second layer on or below the first layer, and a third layer on or above the second layer, wherein a width of the first layer in the vertical direction decreases and then increases, along a direction from the first channel patterns to the second channel patterns.

A semiconductor device includes a first channel region above a substrate, a first metal gate structure engaging the first channel region, a first gate sidewall spacer disposed on sidewalls of the first metal gate structure, a second channel region above the substrate, a second metal gate structure engaging the second channel region, a second gate sidewall spacer disposed on sidewalls of the second metal gate structure, a first interposing feature disposed adjacent to the first channel region, a first epitaxial feature disposed on the first interposing feature and abutting the first channel region, a second interposing feature disposed adjacent to the second channel region, and a second epitaxial feature disposed on the second interposing feature and abutting the second channel region. A bottom surface of the second epitaxial feature is above a bottom surface of the first epitaxial feature.