A semiconductor device includes a lower interlayer insulating layer, a first plurality of bottom nanosheets, a first plurality of upper nanosheets, an upper isolation layer between the first plurality of bottom nanosheets and the first plurality of upper nanosheets, a first bottom gate electrode on the lower interlayer insulating layer, a first upper gate electrode on an upper surface of the first bottom gate electrode, and a first active cut that extends into each of the first bottom gate electrode and the first plurality of bottom nanosheets in the vertical direction and is on an upper surface of the lower interlayer insulating layer, where the first active cut is spaced apart from the first upper gate electrode in the vertical direction, and where the first active cut at least partially overlaps each of the first upper gate electrode and the first plurality of upper nanosheets in the vertical direction.

A semiconductor device includes: a first transistor including a first gate structure; a second transistor including a second gate structure and arranged adjacent to the first transistor in a first direction; and a first isolation feature extending in a second direction. The second direction and the first direction are perpendicular. The first isolation feature is between the first gate structure and the second gate structure and in contact with the first gate structure and the second gate structure. The semiconductor structure further includes a first connection structure under the first isolation feature. The first connection structure connects the first gate structure to the second gate structure.

A semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a plurality of lower nanosheets stacked on the active pattern and spaced apart from each other in a vertical direction, a nanosheet isolation layer including an insulating material on an upper surface of an uppermost nanosheet of the plurality of lower nanosheets, a plurality of upper nanosheets stacked on an upper surface of the nanosheet isolation layer and spaced apart from each other in the vertical direction, a gate electrode extending in a second direction different from the first direction on the active pattern, the gate electrode extending on the plurality of lower nanosheets, the nanosheet isolation layer, and the plurality of upper nanosheets, and an inner spacer on opposing sidewalls of the gate electrode between either adjacent ones of the upper nanosheets, or adjacent ones of the lower nanosheets.

A semiconductor device includes a substrate, a transistor stack on the substrate, a first source/drain structure on a first side of the transistor stack, and a second source/drain structure on a second side of the transistor stack, where the transistor stack includes a lower transistor on the substrate, the lower transistor including a lower channel layer and a lower gate structure surrounding the lower channel layer, an upper transistor on the lower transistor, the upper transistor including an upper channel layer and an upper gate structure surrounding the upper channel layer, and a first connecting layer between the lower gate structure and the upper gate structure, and the first source/drain structure and the second source/drain structure are connected via the first connecting layer.

A method of manufacturing a semiconductor device includes forming an interfacial layer over a channel region and forming a metal-containing layer over the interfacial layer. A metal silicate layer is formed over the channel region after forming the metal-containing layer. A portion of the metal silicate layer is removed. A gate dielectric layer is formed over the channel region after removing the portion of the metal silicate layer, and a gate electrode layer is formed over the gate dielectric layer.

A semiconductor device includes an active pattern extending on a substrate in a first direction, channel patterns vertically stacked on the active pattern, a separation structure extending in a second direction and separating each of the active pattern and the channel patterns into first and second portions, a gate structure extending in the second direction and onto the first portions of the channel patterns, a separation pattern extending in the first direction, separating the first portions of the channel patterns into first and second channel patterns, and separating the gate structure into first and second gate structures, and a third gate structure extending in the second direction and onto the second portions of the channel patterns. The second portions of the channel patterns have a width greater than a sum of first and second widths of the first and second channel patterns, respectively.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.

A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.