In a surface treatment method for a gallium oxide-based semiconductor substrate, a surface of the gallium oxide-based semiconductor substrate is flattened by dry etching with a self-bias of 150 V or more. After the surface of the gallium oxide-based semiconductor substrate is flattened, the surface of the gallium oxide-based semiconductor substrate is washed with a chemical solution containing H.sub.2SO.sub.4 to expose a step terrace structure on the surface of the gallium oxide-based semiconductor substrate.

A drive circuit substrate includes a unit drive circuit including a first transistor including a first semiconductor layer having a first channel region, and a first source region and a first drain region that contain a P-type impurity, a first insulating layer that is provided on the first semiconductor layer, a first-gate-electrode-combined first facing electrode that contains an oxide semiconductor and a conductor impurity and that is provided on the first insulating layer such that the first-gate-electrode-combined first facing electrode overlaps the first channel region in plan view, a first interlayer insulating film that is provided on the first-gate-electrode-combined first facing electrode, a second facing electrode that is provided on the first interlayer insulating film such that the second facing electrode overlaps the first-gate-electrode-combined first facing electrode in plan view, a first drain electrode, a first source electrode, and a holding capacitor.

The present disclosure generally relates to the field of semiconductor devices. More particularly, it relates to a method for producing an electrode contact layer comprising a metal oxide film and a metal film liner, related devices and systems for producing the same.

Provided is a semiconductor device including: at least a semiconductor layer having a corundum structure, the semiconductor layer including a first surface having at least a first side and a second side shorter than the first side, the first surface being a c-plane or an m-plane, a direction of the first side being a direction of a c-axis or a direction of an m-axis.

The present inventive concept provides a method of manufacturing an oxide transistor, the method comprising: a step of forming a first channel layer by supplying a gas containing indium (In) and zinc (Zn) and supplying a gas containing oxygen; a step of forming a spacer on the first channel layer by supplying a gas containing gallium (Ga) and supplying a gas containing oxygen; and a step of forming a second channel layer on the spacer by supplying a gas containing indium (In) and zinc (Zn) and supplying a gas containing oxygen, and an oxide transistor made by the method.

Disclosed are highly integrated memory cells and a semiconductor device including the highly integrated memory cells. The semiconductor device includes a first pillar and a second pillar spaced apart from each other by a shield trench, each pillar including an inner side that defines inner walls of the shield trench and an outer side that faces the inner side; a shield gate formed in the shield trench; a first main gate formed on the outer side of the first pillar; a second main gate formed on the outer side of the second pillar; a bit line formed on lower portions of the first and second pillars; and a capacitor formed on an upper portion of each of the first and second pillars.

The present invention relates to an oxide semiconductor memory device with a dual channel structure and a manufacturing method thereof, and more particularly, to an oxide semiconductor memory device with a dual channel structure including a polysilicon channel in addition to an oxide semiconductor channel, and a manufacturing method thereof. The present invention is to achieve high mobility characteristics of an oxide semiconductor channel and simultaneously implement an erase operation by using an oxide semiconductor channel and a polysilicon channel together.

A semiconductor device fabrication method may comprise: alternately and sequentially stacking a source/drain electrode layer forming a source/drain and a channel layer forming an oxide semiconductor channel; stacking a mask layer to surround a portion where a source/drain region is to be formed; exposing a channel layer of a channel region by etching and removing the source/drain electrode layer of the channel region exposed through the mask layer; and sequentially forming a gate dielectric layer and at least one gate electrode layer on the exposed channel layer of the channel region and on exposed lateral sides of the source/drain electrode layer of the source/drain region.

A semiconductor device includes: a first conductor layer; a second conductor layer; an oxide semiconductor layer provided between the first conductor layer and the second conductor layer; a gate electrode provided next to the oxide semiconductor layer; and a gate insulating film provided between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes at least one of indium, gallium, zinc, aluminum, tin, titanium, silicon, germanium, copper, arsenic, and tungsten and oxygen and includes a first end and a second end. The first conductor layer includes indium, tin, oxygen, and a first element that is at least one of nitrogen, sulfur, selenium, tellurium, hafnium, tantalum, tungsten, rhenium, osmium, iridium, bismuth, lanthanum, yttrium, zinc, cadmium, and mercury. The first end of the oxide semiconductor layer is in contact with the first conductor layer.

According to one embodiment, a semiconductor memory device includes a first capacitor including a first electrode, a second electrode, and a first capacitor insulating film provided between the first electrode and the second electrode, and a first transistor including a first oxide semiconductor layer electrically connected to the second electrode and extending in a first direction, a first gate electrode provided next to the first oxide semiconductor layer, and a third electrode electrically connected to the first oxide semiconductor layer and provided on the opposite side of the second electrode. The second electrode includes a first portion, a second portion provided between the first portion and the first oxide semiconductor layer, and a third portion provided between the second portion and the first oxide semiconductor layer. A first width of the first portion in a second direction perpendicular to the first direction is smaller than a second width of the second portion in the second direction, and a third width of the third portion in the second direction is smaller than the second width.