The present disclosure relates to a semiconductor device including an n-type gallium oxide semiconductor layer that has a center region and a peripheral region having a lower donor density than the center region, an electrode layer that is laminated on the n-type gallium oxide semiconductor layer, and forms Schottky junction with the n-type gallium oxide semiconductor layer in the center region as viewed from a lamination direction, and a first p-type nickel oxide semiconductor layer that is laminated on the n-type gallium oxide semiconductor layer such that the first p-type nickel oxide semiconductor layer is partially positioned between the n-type gallium oxide semiconductor layer and the electrode layer, and has an outer peripheral end portion on a peripheral region side in the peripheral region as viewed from the lamination direction.

A method of manufacturing a semiconductor device including a tin oxide semiconductor having a pn junction between a source electrode and a drain electrode, the method including, changing a conductivity type of a portion of a layer made of the tin oxide semiconductor to form the pn junction.

A transistor, an integrated semiconductor device, and methods of making the same are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.

Provided is a semiconductor element including: a multilayer structure including: a conductive substrate; and an oxide semiconductor film arranged directly on the conductive substrate or over the conductive substrate via a different layer, the oxide semiconductor film including an oxide, as a major component, having a corundum structure, the conductive substrate having a larger area than the oxide semiconductor film.

A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.

Provided is an electronic device including a semiconductor substrate, a single-crystal first transition metal oxide layer on the semiconductor substrate, and a single-crystal second transition metal oxide layer spaced apart from the semiconductor substrate with the single-crystal first transition metal oxide layer interposed therebetween. The first transition metal oxide layer and the second transition metal oxide layer are in contact with each other. The semiconductor substrate, the first transition metal oxide layer, and the second transition metal oxide layer include different materials from each other. The first transition metal oxide layer and the second transition metal oxide layer have the same crystal direction.

A semiconductor device comprising: a bit line extending in a first horizontal direction on a substrate; a channel layer on the bit line, including an oxide semiconductor material that includes indium (In), a first vertical portion, a horizontal portion on the first vertical portion, and a second vertical portion on the horizontal portion; a gate dielectric layer in contact with a first sidewall of the first vertical portion of the channel layer and a lower surface of the horizontal portion of the channel layer; a word line on an inner sidewall and a lower surface of the gate dielectric layer, extending in a second horizontal direction; contact structures, wherein at least one of the contact structures is in contact with the horizontal portion and the second vertical portion of the channel layer; and a capacitor structure on the at least one of the contact structures.

Disclosed herein is a Schottky barrier diode that includes a semiconductor substrate and a drift layer made of gallium oxide, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has a trench at a position overlapping the anode electrode. The trench is covered at least at its bottom surface with a laminated insulating film and filled with a conductive material connected to the anode electrode. The laminated insulating has a structure in which first and second insulating films made of mutually different insulating materials are laminated. The insulating materials constituting the first and second insulating films have a bandgap equal to or higher than a bandgap of gallium oxide and have a dielectric constant equal to or higher than of a dielectric constant of gallium oxide.

In a metal-oxide-semiconductor chip device first and second source structures are provided on a first side of the semiconductor substrate as a pair. The drain structure is provided on a second side of the semiconductor substrate. The second side faces away from the first source structure and the second source structure. A first channel structure is provided between and separates the first source structure and the semiconductor substrate. A second channel structure is provided between and separates the second source structure and the semiconductor substrate. A gate structure is provided on the first side of the semiconductor substrate. The first and second channel structures are configured as mirror images of each other, and a wide-width area and a narrow-width area are formed between the first and second channel structures as a result of varied spacing between the first and second channel structures.

A semiconductor device includes an oxide semiconductor layer, a gate electrode arranged apart from the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The gate insulating layer includes a plurality of layers with different energy bandgaps. The gate insulating layer includes a plurality of first insulating layers arranged apart from each other in a thickness direction of the gate insulating layer, a second insulating layer between a first set of adjacent first insulating layers and having a smaller energy bandgap than each first insulating layer, and a third insulating layer between a second set of adjacent first insulating layers and having a greater energy bandgap than each first insulating layer. The third insulating layer is closer to the oxide semiconductor layer than the second insulating layer.