A transistor with improved low-frequency noise characteristics is disclosed. Phase complexing channel layer having quantum dots distributed within an amorphous matrix is formed, and a surface stabilization layer is formed in contact with the phase complexing channel layer. The surface stabilization layer has a repeating structure of an inorganic insulating layer and an organic shielding layer. Since the quantum dots of the phase complexing channel layer are in a quantized state, carriers trapped in the quantum dots are limited. Even if current is generated at the phase complexing channel layer by the drain-source voltage, the carriers trapped at the quantum dots are maintained at a constant level. Accordingly, the drain-source current is constant even when the gate voltage increases, and the noise component of the gate voltage is not reflected in the drain current.

A semiconductor device manufacturing method includes forming a tin-containing oxide film on a gallium-oxide-based compound; irradiating the tin-containing oxide film with ultraviolet laser light to dope the gallium-oxide-based compound with tin; and forming a metal electrode on the tin-containing oxide film irradiated with the ultraviolet laser light.

A semiconductor device may include a first gate electrode and a second gate electrode spaced apart from each other on a substrate, a first channel layer on one side of the first gate electrode, a second channel layer on one side of the second gate electrode, and a third gate electrode connecting the first gate electrode and the second gate electrode to each other. The first channel layer and the second channel layer may extend in a first direction and the first direction may be perpendicular to the substrate.

The present disclosure provides a method for operating a ferroelectric field effect transistor (FeFET) as a capacitive memory device. The method comprises connecting a source terminal and a drain terminal of the FeFET together, applying a small-signal voltage to a gate terminal of the FeFET at zero direct-current gate voltage, and measuring capacitance between the gate terminal and the connected source and drain terminals to determine a capacitance state of the FeFET. The capacitance state corresponds to either a high capacitance state or a low capacitance state based on polarization of a ferroelectric gate stack of the FeFET. The disclosure also provides a FeFET device configured for capacitive memory operation comprising a semiconductor channel, a ferroelectric gate stack disposed over the semiconductor channel, a gate terminal connected to the ferroelectric gate stack, a source terminal and a drain terminal connected to the semiconductor channel, and a body terminal. The FeFET device is configured to operate in a capacitive read-out mode where capacitance is measured between the gate terminal and connected source and drain terminals at zero direct-current gate voltage to determine a memory state.

Provided is an electrochemical memory device including a channel layer extending in a vertical direction, the channel layer including a semiconductor oxide, a gate electrode surrounding at least a portion of a side surface of the channel layer, a reservoir layer between the channel layer and the gate electrode, and a gate oxide layer between the gate electrode and the reservoir layer, and wherein the channel layer includes a first channel layer and a second channel layer, the second channel layer spaced farther apart from the gate electrode than the first channel layer, and an oxygen dissociation energy of the first channel layer may be lower than an oxygen dissociation energy of the second channel layer.

A semiconductor memory device semiconductor memory device includes a substrate, a plurality of wordlines stacked in a first direction on the substrate, channel regions between adjacent wordlines in the first direction and extending in a second direction, first source/drain regions on first sides of the channel regions, second source/drain regions on second sides of the channel regions, bitlines extending in the first direction on the substrate and connected to corresponding ones of the first source/drain regions, respectively, data storage elements connected to the second source/drain regions, respectively, and capping films between the second source/drain regions and corresponding ones of the data storage elements, respectively, the capping filing including insertion holes, respectively, wherein at least portions of the second source/drain regions are inserted into corresponding ones of the insertion holes of the capping films, respectively.

A semiconductor memory device includes a bitline extending in a first direction; a first channel pattern on an upper surface of the bitline; a second channel pattern on the upper surface of the bitline; a first wordline extending in a second direction; a second wordline extending in the second direction; a first capacitor and a second capacitor connected to the first channel pattern and the second channel pattern, respectively; a first gate insulating pattern; a second gate insulating pattern ; a first ruthenium structure between the first channel pattern and the first capacitor; and a second ruthenium structure between the second channel pattern and the second capacitor, wherein an uppermost surface of the first gate insulating pattern is provided without the first ruthenium structure provided thereon, and an uppermost surface of the second gate insulating pattern is provided without the second ruthenium structure provided thereon.

A memory system including a memory cell array and a control circuit, the memory device includes a ferroelectric layer with a thickness of 3 nm or more and 7 nm or less, when the control circuit determines a number of times of executions of a program for the memory cell reaches a predetermined number of times, the control circuit applies a first positive pulse voltage having a pulse width of a (sec) m times to the ferroelectric layer, and applies a second negative pulse voltage having a pulse width of b (sec) n times to the ferroelectric layer so that Equation 1 and Equation 2 hold.

[00001]$\begin{array}{cc}0.1\sec am<250\sec & \left(\mathrm{Equation}1\right)\end{array}$$\begin{array}{cc}0.1\sec bn<250\sec .& \left(\mathrm{Equation}2\right)\end{array}$

The present disclosure provides a precursor composition for deposition of a thin film including liquid indium precursor, liquid gallium precursor and liquid zinc precursor, a manufacturing method of the thin film by using the precursor composition, the thin film manufactured by using the precursor composition and an electronic device including the thin film.

A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device is provided. The semiconductor device may include a first sub-cell array including first memory cells that are vertically stacked; a second sub-cell array including second memory cells that are horizontally adjacent to the first memory cells, the second memory cells being vertically stacked; a linear opening horizontally extending between the first sub-cell array and the second sub-cell array; and a vertical conductive line formed in the linear opening, the vertical conductive line being electrically coupled to the first memory cells and the second memory cells that are horizontally adjacent to each other.