An epitaxial wafer 1 includes a Ga.sub.2O.sub.3-based substrate, a metal layer, and a -Ga.sub.2O.sub.3 layer. The Ga.sub.2O.sub.3-based substrate has a first principal surface and a second principal surface opposite from the first principal surface. The metal layer is formed on the first principal surface of the Ga.sub.2O.sub.3-based substrate. The metal layer has a plurality of openings. The -Ga.sub.2O.sub.3 layer covers the first principal surface of the Ga.sub.2O.sub.3-based substrate and the metal layer. The metal layer is made of a material such as a noble metal or a refractory metal. The thickness of the -Ga.sub.2O.sub.3 layer is smaller than the thickness of the Ga.sub.2O.sub.3-based substrate.

The method includes: providing an initial structure including a plurality of dielectric layers and a plurality of conductive layers, where each of the plurality of conductive layers includes a plurality of conductive strips, a plurality of first holes penetrate through the plurality of conductive strips along a first direction; laterally thinning the plurality of conductive strips to form a plurality of first trenches; forming a plurality of first indium gallium zinc oxides in the plurality of first trenches; laterally thinning the plurality of dielectric layers to expose part of the plurality of first indium gallium zinc oxides; forming a plurality of second indium gallium zinc oxides on the surfaces of the plurality of exposed first indium gallium zinc oxides, where the concentration of indium in the plurality of first indium gallium zinc oxides is higher than that of indium in the plurality of second indium gallium zinc oxides.

According to one embodiment, a semiconductor device include first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The first conductive member is electrically connected to the second electrode. The first conductive member includes a first conductive portion and a second conductive portion. A first distance between the first electrode and the first conductive portion is shorter than a second distance between the first electrode and the first portion. The semiconductor member is provided between the first electrode and the second electrode.

A semiconductor device may include a lower electrode, a channel on the lower electrode, a gate insulating layer on the channel, a gate electrode on the gate insulating layer, and an upper electrode on the gate electrode. The lower electrode may include a doped region. The doped region may include In or Nb. The upper electrode, the channel, and the lower electrode may be spaced apart from each other in a direction perpendicular to the lower electrode.

Provided are a semiconductor device, an electronic apparatus including the semiconductor device, and/or a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, an oxide semiconductor layer on the substrate, a first electrode on the oxide semiconductor layer, a second electrode on the oxide semiconductor layer and apart from the first electrode, and a first layer, a second layer, and a third layer in at least one of a region between the oxide semiconductor layer and the first electrode and a region between the oxide semiconductor layer and the second electrode. The second layer includes at least one selected from tantalum oxide, niobium oxide, strontium oxide, and aluminum oxide.

A semiconductor device may include a substrate and a Dirac source transistor. The Dirac source transistor may include a gate electrode on the substrate, a gate dielectric film covering the gate electrode, a semiconductor channel layer including an oxide semiconductor material and covering the gate dielectric film, a Dirac source layer partially covering the semiconductor channel layer, a source electrode connected to the Dirac source layer, and a drain electrode connected to the semiconductor channel layer. The Dirac source layer may at least partially overlap the gate electrode in a vertical direction. The Dirac source layer may be spaced apart from the drain electrode and may be not connected to the drain electrode.

High electron mobility transistors are provided which comprise a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween.

A power semiconductor structure is provided. The power semiconductor structure comprises a metal oxide semiconductor layer disposed on the gallium-containing oxide substrate. A thermal inner trench surrounds the gallium-containing oxide semiconductor layer and is disposed on the gallium-containing oxide substrate. A metal substrate is thermally connected to the thermal inner trench, and at least one pair of a P-type and an N-type semiconductor material are respectively connected to two ends of the metal substrate. When an external current flows into the N-type semiconductor material and flows through the metal substrate to the P-type semiconductor material, the heat energy generated by the gallium-containing oxide semiconductor layer is absorbed by the metal substrate through the thermal inner trench, and then dissipated by opposite ends of the P-type and the N-type semiconductor material opposite to the metal substrate.

A single crystal growth method for growing a single crystal of a gallium oxide-based semiconductor, the method including growing the single crystal from a melt of a raw material of the single crystal in an oxidizing atmosphere. Density and average length of voids in the single crystal are controlled by a relative value of an Si concentration and an Sn concentration in the single crystal.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes first to fifth circuits. Each of the first to fourth circuits includes first and second cells, a sixth circuit, first and second current generation circuits, a first input terminal, and a second output terminal. The first circuit to the fourth circuit are electrically connected to each other in a ring, and the first circuit is electrically connected to the fifth circuit. In each of the first to fourth circuits, the first cell is electrically connected to the second cell through the first wiring, the first current generation circuit, and the third wiring, and is electrically connected to the first input terminal and the sixth circuit through the second wiring. The second cell is electrically connected to the first output terminal through the second current generation circuit. Note that the first current generation circuit functions as a current mirror circuit, and the second current generation circuit functions as an arithmetic circuit of a function system. The first cell performs an arithmetic operation of a product, and the second cell retains the result of the arithmetic operation.