An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.

The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

A method for forming a semiconductor structure is provided. The method includes alternately stacking channel layers and sacrificial layers on a substrate in a vertical direction to form a semiconductor stack, patterning the semiconductor stack to form a fin-shaped structure protruding from the substrate, forming a source/drain trench in the fin-shaped structure, laterally recessing the sacrificial layers in the fin-shaped structure to form first recesses, and enlarging the first recesses to form second recesses. One of the second recesses has a vertical dimension greater than a thickness of the sacrificial layer after enlarging the first recesses. The method further includes forming inner spacers in the second recesses, and forming a source/drain feature in the source/drain trench.

A semiconductor device may include: a lower insulating pattern including a first surface, a second surface opposite to the first surface in a first direction, and a sidewall connecting the first surface to the second surface; a first sheet pattern in contact with the first surface of the lower insulating pattern; a second sheet pattern on the first sheet pattern, spaced apart from the first sheet pattern in the first direction; a gate structure including an inner gate structure, the inner gate structure being between the first sheet pattern and the second sheet pattern, extending in a second direction, and including a gate electrode and a gate insulating film; a source/drain pattern connected to the first sheet pattern and the second sheet pattern; and a bottom insulating spacer below the source/drain pattern in the first direction, and overlapped with the source/drain pattern in the first direction.

A method for manufacturing a co-integrated semiconductor structure from a first and a second layer stack is provided. The first layer stack includes a channel layer and a sub-stack. Each sub-stack includes a sacrificial layer of a first type, a first slender layer on the sacrificial layer of the first type, a sacrificial layer of a second type, a second slender layer, a further sacrificial layer of the first type, and a further channel layer on the further sacrificial layer of the first type. The second layer stack includes a channel layer and a sub-stack. Each sub-stack includes a sacrificial layer of the first type and a further channel layer on the sacrificial layer of the first type. A separation between the neighboring channel layers of the first layer stack is larger than a separation between neighboring channel layers of the second layer stack.

A semiconductor device may include a gate structure, a plurality of channel patterns spaced apart from each other in a first direction, each of the plurality of channel patterns extending through the gate structure in a second direction substantially perpendicular to the first direction, a source/drain layer adjacent to the gate structure in the second direction, the source/drain layer contacting the plurality of channel patterns, a first spacer on a sidewall of the gate structure in the second direction and including an insulating material, and a second spacer on a sidewall of the first spacer in the second direction, the second spacer contacting the source/drain layer. The first spacer may include opposite edge portions in the first direction and a center portion in the first direction, and a width of the first spacer in the second direction may increase from the opposite edge portions toward the center portion.