A semiconductor device includes a substrate, a metal gate and a poly gate. The substrate includes a first region and a second region. The metal gate is disposed on the first region of the substrate. The poly gate is disposed on the second region of the substrate. A gate area of the poly gate is greater than that of the metal gate.

An integrated circuit includes a transistor having a plurality of stacked channels each extending between the source/drain regions of the transistor. The transistor also includes a hard mask nanostructure above the highest channel and extending between the source/drain regions of the transistor. A gate dielectric and gate metals wrap around the channels and the hard mask nanostructure.

Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source/drain region and a second source/drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source/drain region, a second leakage block layer over the second source/drain region, a dielectric layer on the first leakage block layer, a first source/drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.

Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The method includes forming a fin structure from a substrate, and the fin structure includes a plurality of semiconductor layers. The method further includes depositing a gate dielectric layer around a portion of each semiconductor layer of the plurality of semiconductor layers, depositing an adhesion layer on the gate dielectric layer, and the adhesion layer surrounds the portion of each semiconductor layer of the plurality of semiconductor layers. The method further includes depositing a fluorine-containing layer on the adhesion layer, and the fluorine-containing layer surrounds the portion of each semiconductor layer of the plurality of semiconductor layers. The method further includes performing an annealing process on the fluorine-containing layer, removing the fluorine-containing layer and the adhesion layer, and forming a gate electrode layer on the gate dielectric layer.

A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.

A semiconductor device includes an active area on a substrate, a gate insulating layer on the active area, and a gate electrode structure on the gate insulating layer. The gate electrode structure includes a first blocking impurity-doped layer in contact with an upper surface of the gate insulating layer and doped with a blocking impurity, a middle layer on the first blocking impurity-doped layer, and a second blocking impurity-doped layer on the middle layer and doped with the blocking impurity. A blocking impurity concentration in the second blocking impurity-doped layer is higher than a blocking impurity concentration in the first blocking impurity-doped layer.

The present disclosure relates to a gate all around (GAA) device made based on a GAA transistor structure that comprises a stack of multiple semiconductor channel layers and one or more first gate layers alternatingly arranged along a first direction. Each channel layer is encapsulated by a gate dielectric layer, and each first gate layer is arranged between two channel layers following another. The GAA transistor structure further comprises two second gate layers sandwiching the stack in a second direction and connected to the first gate layers. Each first gate layer is made of a first work function metal structure and each second gate layer is made of a second work function metal structure that is different from the first work function metal structure. Each first gate layer has a first thickness and each second gate layer has a second thickness larger than the first thickness.

A method of manufacturing a semiconductor device includes forming an interfacial layer over a channel region and forming a metal-containing layer over the interfacial layer. A metal silicate layer is formed over the channel region after forming the metal-containing layer. A portion of the metal silicate layer is removed. A gate dielectric layer is formed over the channel region after removing the portion of the metal silicate layer, and a gate electrode layer is formed over the gate dielectric layer.

Embodiments of the invention include forming a first transistor having first nanosheets, first dipole gate dielectric material being formed around the first nanosheets. An aspect includes forming a second transistor comprising second nanosheets, second dipole gate dielectric material being formed around the second nanosheets, the first and second transistors being in a vertical stack, a first spacing between the first nanosheets being different from a second spacing between the second nanosheets. An aspect includes forming a workfunction metal stack having a first workfunction metal and a second workfunction metal, the first and second workfunction metals being formed between the first nanosheets, the first workfunction metal being formed to pinch off in the second spacing between the second nanosheets such that the second workfunction metal is absent in the second spacing between the second nanosheets.

A semiconductor device includes a substrate including an active region extending in a first direction, gate structures extending in a second direction overlapping the active region, on the substrate, and spaced apart from each other in the first direction, a blocking gate structure overlapping the active region, between the gate structures, and extending in the second direction, source/drain regions disposed in a region in which the active region is recessed, on both sides of the blocking gate structure, a backside contact structure disposed below at least one of the source/drain regions, and backside blocking structures disposed below the gate structures and the blocking gate structure, respectively. The blocking gate structure includes a first element different from the gate structures.