A semiconductor device fabrication method is provided and includes forming first and second stacks each including a dual layer top dielectric cap (TDC), sequentially surrounding each layer and a portion of the dual layer TDC of the first stack with high-k dielectric, a first work function metal (WFM) and a second WFM, sequentially surrounding each layer and a portion of the dual layer TDC of the second stack with the high-k dielectric and the second WFM, forming gate metal around the first and second stacks and recessing the gate metal and the second WFM to a depth defined above a height of an uppermost first WFM horizontal portion.

Provided is a semiconductor device which includes: a 1.sup.st transistor structure including a 1.sup.st n-type field-effect transistor (NFET) and a 1.sup.st p-type field-effect transistor (PFET) vertically thereabove, the 1.sup.st NFET having a greater channel width than the 1.sup.st PFET; and a 2.sup.nd transistor structure including a 2.sup.nd PFET and a 2.sup.nd NFET vertically thereabove, the 2.sup.nd PFET having a greater channel width than the 2.sup.nd NFET.

A field effect transistor structure is disclosed. The field effect transistor structure includes: a fin-shaped channel protruding from a substrate and extending in one direction; a source electrode on one side of the fin-shaped channel; a drain electrode separated from the source electrode with the fin-shaped channel therebetween; a gate insulating film surrounding side and upper surfaces of the fin-shaped channel; a gate electrode on the gate insulating film; and a two-dimensional semiconductor material layer between the gate insulating film and the gate electrode.

A transistor may include a gate structure on a substrate, the gate structure including a first gate dielectric pattern including a first metal oxide. A gate electrode includes a lower portion with a second metal oxide doped with tetravalent and pentavalent elements or with a metal oxynitride doped with the tetravalent and pentavalent elements. The gate electrode includes an upper portion on the lower portion with a metal doped with the tetravalent and pentavalent elements or a metal nitride doped with the tetravalent and pentavalent elements and a source/drain region at an upper portion of the substrate adjacent to the gate structure.

The present disclosure discloses a method for fabricating an integrated structure of a metal-gate MOS transistor, which defines a high-resistance MOS device gate structure region in the high-resistance device area and a high-voltage MOS device gate structure region in the high-voltage device area through photolithography, wherein during gate polysilicon etching, the entire high-voltage MOS device gate structure region is retained without forming slots in the MOS device gate structure regions; spacers are formed through self-aligned etching, eliminating the need for a spacers process mask; and the same mask layer is used for both the high-resistance layer etching and the slot etching in the high-voltage MOS device gate structure region. This fabricating method offers several advantages: reduced number of required masks, healthier high-voltage MOS device gate structures, larger process windows, improved device electrical characteristics, enhanced reliability, and simplified contact hole etching process with lower contact resistance.