The present inventive concept relates to an RGB micro-light-emitting diode having a vertically-stacked structure with corner mesa contact structures, and a manufacturing method thereof. The RGB micro-light-emitting diode having a vertically-stacked structure with corner mesa contact structures includes an n-type contact electrode layer, a first light-emitting structure, a common electrode layer, a second light-emitting structure, a tunnel junction layer, and a third light-emitting structure, which are sequentially stacked on a substrate. The RGB micro-light-emitting diode with a reduced unit area can be easily manufactured by forming the corner mesa contact structure on each of the n-type contact electrode layers by etching the vertically-stacked structure, forming contact structures on the n-type contact electrode layers, followed by electrical connection.

A semiconductor structure includes a plurality of gate-all-around field effect transistors, each of the gate-all-around field effect transistors including: first and second source-drain regions; a plurality of nanowire channels interconnecting the first and second source-drain regions; and a common gate. The common gate includes an upper gate portion above the plurality of nanowire channels and a lower gate portion surrounding the plurality of nanowire channels. A unitary spacer structure includes an upper spacer portion between the upper gate portion and the first and second source-drain regions and a lower spacer portion between the lower gate portion and first and second source-drain regions. The upper spacer portion and the lower spacer portion have aligned left and right edges.

A semiconductor device includes switches including nano sheets and horizontal conductive lines surrounding the nano sheets. The semiconductor device includes first contact nodes formed on first edges of the nano sheets, and vertical conductive lines including pyramid portions surrounding the first contact nodes. Each of the vertical conductive lines is coupled to a corresponding one of the nano sheets. The semiconductor device includes data storage devices each coupled to a corresponding one of second edges of the nano sheets. The semiconductor device includes a supporter surrounding the vertical conductive lines.

A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns spaced apart from the first lower pattern in a first direction, a first gate structure including first inner gates between the first lower pattern and a lowermost first sheet pattern of the first sheet patterns, and between each pair of adjacent first sheet patterns, the first inner gates extending in a second direction that intersects the first direction, where each of the first inner gates includes a first gate electrode and a first gate insulating film, first source/drain patterns on the first lower pattern and connected to the first sheet patterns, first inner spacers between the first source/drain patterns and the first inner gates, and first nitrogen build-up areas within the first inner spacers.

The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p/n/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n/p/n+ structures. The disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type, and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.

A semiconductor device may include: a field insulating layer; a first gate electrode disposed on the field insulating layer; a plurality of first nanosheets disposed in the first gate electrode; a second gate electrode disposed on the field insulating layer and forming a boundary with the first gate electrode; a plurality of second nanosheets disposed in the second gate electrode; and a gate pattern bridge disposed between the first gate electrode and the second gate electrode and contacting the boundary.

A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.