A semiconductor device structure and methods of forming the same are described. The structure includes a first semiconductor layer disposed over a substrate, the first semiconductor layer has an edge portion and a center portion, and a height of the center portion is substantially greater than a height of the edge portion. The structure further includes a dielectric spacer disposed below and in contact with the edge portion of the first semiconductor layer, a gate dielectric layer surrounding the center portion of the first semiconductor layer, and a gate electrode layer disposed on the gate dielectric layer surrounding the center portion of the first semiconductor layer.

Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.

A semiconductor device and fabrication method are described for integrating I/O and core nanosheet transistors in a single nanosheet process flow by processing a stack of alternating first and second semiconductor structures formed on a substrate, where the first semiconductor structures located over a I/O thick oxide transistor region include a planar semiconductor channel layer sandwiched between upper and lower dielectric layers, and where the alternating first and second semiconductor structures are processed to form gate-all-around electrodes in a core transistor stack that are connected over a relatively thinner gate dielectric layer to control one or more first planar semiconductor channel layers in the core transistor stack, and to form gate-all-around electrodes in an I/O transistor stack that are connected over a relatively thicker gate dielectric layer to control one or more second planar semiconductor channel layers in the I/O transistor stack.

The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a stack of channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shape structure, forming a dummy gate stack over a channel region of the fin-shape structure, recessing a source/drain region to form a source/drain trench, forming an epitaxial feature in the source/drain trench, after the forming of the epitaxial feature removing the dummy gate stack, releasing the channel layers in the channel region as channel members, forming a gate structure wrapping around each of the channel members, and after the forming of the gate structure performing an ion implantation to increase a dopant concentration of a dopant in the epitaxial feature.

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a fin-shape base protruding from a semiconductor substrate. A top surface of the semiconductor substrate is in a (100) crystal plane, and a top surface of the fin-shape base is in a (110) crystal plane. The semiconductor device also includes channel members disposed over the top surface of the fin-shape base, a gate structure wrapping around at least one of channel members, a gate spacer extending along a sidewall of the gate structure, a source/drain feature abutting the channel members, and a dopant-free epitaxial feature under the source/drain feature. A top surface of the source/drain feature is in a (110) crystal plane. A top surface of the dopant-free epitaxial feature is in a (110) crystal plane.

A method of forming a semiconductor device includes: forming a gate structure over a fin; forming an interlayer dielectric (ILD) layer over the fin around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the fin, where the first and second dielectric plugs cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first and second dielectric plugs; etching, using the patterned mask layer as an etching mask, the segment of the gate structure using an isotropic etching process to form a recess in the gate structure; extending the recess into the fin by performing an anisotropic etching process; and after extending the recess, filling the recess with a dielectric material.

An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.

The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Nanostructure channels of a nanostructure transistor are etched during a nanosheet release process for removing sacrificial nanostructure layers between the nanostructure channels. The nanostructure channels are etched such that the thickness of the nanostructure channels at the edges of the nanostructure channels is less than the thickness of the nanostructure channels at the centers of the nanostructure channels. This results in the nanostructure channels having a sloped/tapered or curved cross-sectional profile between the centers and the edges of the nanostructure channels. The resultant cross-section profile provides larger openings between vertically adjacent nanostructure channels for depositing material of a gate structure of the nanostructure transistor between vertically adjacent nanostructure channels of the nanostructure transistor. The larger openings increase the gap-filling performance for forming the gate structure, which reduces the likelihood of (and/or size of) seams and/or voids in the gate structure between vertically adjacent nanostructure channels.