A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.

An apparatus including a planar metal oxide semiconductor field-effect transistor and a planar Schottky barrier diode that are physically and functionally integrated into a single, continuous structure, and a method of making such an apparatus. The planar Schottky barrier diode is located over a junction field-effect transistor neck region which is adjacent to the planar metal oxide semiconductor field-effect transistor in a single, continuous volume of semiconductor material. The planar metal oxide semiconductor field-effect transistor may include first and second transistor sides spaced apart at respective first and second sides of the volume of semiconductor material, in which case the junction field-effect transistor neck region and the planar Schottky barrier diode are located between the first and second transistor sides.