Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.

A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.