H10D62/883

TRENCH-SHAPED TERNARY CMOS DEVICE
20250254905 · 2025-08-07 ·

A trench-shaped ternary CMOS device includes a common drain provided at the bottom, a 2D phase change material layer composed of a 2D phase change material and stacked on the top of the common drain, a common gate provided over the 2D phase change material layer, a 2D n-type channel semiconductor material layer that is vertically stacked with respect to the 2D phase change material layer and connected to one end of the 2D phase change material layer and that has one side surface that faces one end of the common gate, and a 2D p-type channel semiconductor material layer that is vertically stacked with respect to the 2D phase change material layer and connected to an opposite end of the 2D phase change material layer and that has one side surface that faces an opposite end of the common gate.

METHOD OF PREPARING TELLURIUM OXIDE THIN FILM AND THIN FILM TRANSISTOR USING SPUTTERING
20250253150 · 2025-08-07 ·

Disclosed is a method of preparing a tellurium oxide thin film and a thin film transistor using sputtering. In detail, a method of preparing the semiconductor thin film, the method comprising: (a) providing a target comprising a chalcogen atom and a tellurium atom (Te) comprising at least one selected from the group consisting of sulfur atoms (S) and selenium atoms (Se); and (b) preparing a semiconductor thin film comprising an amorphous p-type semiconductor by co-deposition on a substrate using the target in an atmosphere of a mixed gas comprising argon gas and oxygen gas by a sputtering method. The semiconductor thin film channel layer according to the present disclosure has the effect of providing a thin film transistor (TFT) exhibiting excellent output/transfer characteristics and excellent electrical performance with high hole field effect mobility and an on/off current ratio of 10.sup.5.

REMOTE DOPING OF A SEMICONDUCTOR STRUCTURE, RELATED DEVICES, RELATED SYSTEMS, AND RELATED METHODS

The technology of the present disclosure generally relates to the field of semiconductor devices. More particularly, it relates to a field-effect transistor (FET) and systems and methods for producing the same. The FET comprising: a substrate; at least one channel layer comprising a channel material; a source electrode and a drain electrode in electrical contact with the channel layer; at least one gate electrode in contact with a gate insulating layer; at least one remote dopant layer in electrical contact with at least a portion of the gate electrode or the gate insulating layer; wherein the remote dopant layer comprises at least one boron-containing material; and wherein the remote dopant layer is configured for remote doping of the channel material of the channel layer.

VERTICAL FIELD EFFECT DEVICE AND METHOD OF MANUFACTURING

The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate and a first electrode configured as either a source or a drain of the transistor. The device includes a second electrode) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion and a gate insulating layer, which is arranged between the active layer and a gate conductor portion as to prevent direct contact between the active layer and the gate conductor portion. The active layer comprises a 1D material arranged with its longitudinal axis parallel to the substrate and/or a 2D material arranged with its plane substantially parallel to the substrate. The present disclosure further comprises a method for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

Electronic device including two-dimensional material and method of manufacturing the same

An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.

Field effect transistor including transition metal dichalcogenide covered with protective layer, and method of manufacturing the same

As a field effect transistor (FET) having a transition metal dichalcogenide capped with a hydrocarbon (HC) protective film according to a preferred embodiment as a channel layer forms a dielectric thin film having a large area of a centimeter scale as a protective film on the surface of the transition metal dichalcogenide, the problem of lowering the electrical performance of the field effect transistor, which is generated due to scattering or trapping of carriers within the channel as impurity molecules such as oxygen, moisture, and the like existing in the surrounding environment are adsorbed on the surface of the transition metal dichalcogenide and act as defects, can be solved, and stability of long-term storage can be improved.

METHOD FOR REGULATING METAL-SEMICONDUCTOR CONTACT BY INTERLAYER ELECTRIC DIPOLES
20250294843 · 2025-09-18 ·

A method for regulating metal-semiconductor contact by interlayer electric dipoles is provided. The method comprises providing a two-dimensional van der Waals superlattice metal material and a two-dimensional semiconductor; testing a surface dipole direction of the two-dimensional van der Waals superlattice metal material; switching a termination surface of the two-dimensional van der Waals superlattice metal material by mechanical peeling as needed; and contacting the required two-dimensional van der Waals superlattice metal material with the two-dimensional semiconductor, and regulating the metal-semiconductor contact by the electric dipole between the two-dimensional van der Waals superlattice metal material and the two-dimensional semiconductor.

TWO-DIMENSIONAL SEMICONDUCTOR MATERIAL-BASED CHARGE SUPER-INJECTION MEMORY AND PREPARATION THEREOF
20250294764 · 2025-09-18 ·

A two-dimensional semiconductor material-based charge super-injection memory, including a substrate, a gate electrode, a blocking layer, a charge-trapping layer, a tunneling layer, a two-dimensional semiconductor channel layer, a drain electrode and a source electrode. The gate electrode is provided above the substrate. The blocking layer is configured to cover the gate electrode and the substrate. The charge-trapping layer is provided on the blocking layer. The tunneling layer is provided on the charge-trapping layer. The two-dimensional semiconductor channel layer is provided on the tunneling layer. The two-dimensional semiconductor channel layer is entirely encompassed within a coverage area of the gate electrode and a coverage area of the tunneling layer. The drain electrode and the source electrode are each partially overlapped with the two-dimensional semiconductor channel layer. A fabrication method of such charge super-injection memory is also provided.

METHOD FOR FORMING A 2D CHANNEL FIELD-EFFECT TRANSISTOR DEVICE
20250311347 · 2025-10-02 ·

A method for forming a 2D channel field-effect transistor device is provided. The method includes forming a device layer stack on a substrate. The device layer stack includes lower and upper sacrificial layers and a channel layer of a 2D material. The method further includes embedding the device layer stack in a dummy layer, forming a gate cavity in the dummy layer, and removing the sacrificial layers from the device layer stack by etching the sacrificial material from the gate cavity. After removing the sacrificial layers, the method includes forming an oxide liner along sidewalls of the gate cavity including an oxidation process to oxidize a thickness portion of the dummy layer, forming a gate stack in the gate cavity to surround the channel layer, forming source/drain contact cavities in the dummy layer, forming source/drain contacts in the source/drain contact cavities, and replacing the dummy layer with a dielectric layer.

SPIN LIGHT EMITTING DEVICE BASED ON TWO-DIMENSIONAL MATERIALS
20250311313 · 2025-10-02 ·

Disclosed is a spin light emitting device based on two-dimensional material. The light emitting device comprises: a two-dimensional structure configured to emit circularly polarized light in response to spin-polarized carrier injection, wherein the two-dimensional structure is a two-dimensional Van der Waals heterostructure; a spin injector configured to inject spin-polarized carriers into the two-dimensional Van der Waals heterostructure, wherein the light emitted by the two-dimensional structure has a circular polarization state determined by the magnetization state of the spin injector; and a magnetization controller configured to change the magnetization state of the spin injector. The spin-based light emitting device emits circularly polarized light or single photons on the basis of two-dimensional material at room temperature without introducing a magnetic field, and has the capability of electrical control.