Provided is a semiconductor device including a substrate, an insulating layer on the substrate, a phase change material structure on the insulating layer, and a first source/drain electrode and a second source/drain electrode disposed on the phase change material structure and spaced apart from each other in a first direction, wherein the phase change material structure includes a plurality of two-dimensional material layers, and an intercalation material between the plurality of two-dimensional material layers.

A halide perovskite-based complementary semiconductor device according to an embodiment of the present invention includes a substrate, a two-dimensional material layer formed on an upper surface side of the substrate and including a hole injection layer and an electron injection layer, a halide perovskite layer formed on the two-dimensional material layer, and an electrode layer formed on the halide perovskite layer and including a drain electrode, an output electrode, and a source electrode.

A semiconductor device and a method of fabricating the same are provided. The semiconductor device may include a source electrode, a drain electrode, an insulating region between the source electrode and the drain electrode, and a channel layer. The channel layer may be on the source electrode, the insulating region, and the drain electrode. The channel layer may include a source region on the source electrode, a drain region on the drain electrode, and a channel region on the insulating region. The source region and the drain region may include a precious metal element. The precious metal element in the drain region may be the same as the precious metal element in the source region. The channel region may include a first two-dimensional material layer having precious metal element-based semiconductor characteristics that may be the same as precious metal element-based semiconductor characteristics of the precious metal element.

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and a memory device including the semiconductor device. The semiconductor device includes a channel layer, an insulating layer on the channel layer, an intermediate electrode on the insulating layer, a mixed layer provided on the intermediate electrode and including a discontinuous ferroelectric and a low-k dielectric material filled between regions of the discontinuous ferroelectric, the low-k dielectric material having a dielectric constant less than a dielectric constant of the discontinuous ferroelectric, a gate electrode on the mixed layer, and a two-dimensional (2D) material layer provided in at least region selected from a region between the intermediate electrode and the mixed layer and a region between the gate electrode and the mixed layer.

A semiconductor device may include a first gate electrode and a second gate electrode spaced apart from each other on a substrate, a first channel layer on one side of the first gate electrode, a second channel layer on one side of the second gate electrode, and a third gate electrode connecting the first gate electrode and the second gate electrode to each other. The first channel layer and the second channel layer may extend in a first direction and the first direction may be perpendicular to the substrate.

The present invention relates to the field of semiconductor devices, specifically addressing challenges in interconnectivity and transistor density. This patent describes a novel method utilizing 2D semiconductors for the creation of monolithic 3D integrated multi-tier circuits on top of an integrated circuit. The invention achieves substantially higher vertical interconnect bandwidth, significantly increased IO density, and orders of magnitude lower signal transmission delay compared to conventional methods like through-silicon via (TSV) or copper-to-copper hybrid bonding. These advancements are made possible by stacking integrated circuit layers monolithically, connecting layers with vias, and utilizing 2D semiconductor-based transistors. Furthermore, the invention allows for a substantial increase in transistor density, contributing to enhanced processing capability. The utilization of more cost-effective process nodes further enhances the economic viability of the invention.

A semiconductor memory device semiconductor memory device includes a substrate, a plurality of wordlines stacked in a first direction on the substrate, channel regions between adjacent wordlines in the first direction and extending in a second direction, first source/drain regions on first sides of the channel regions, second source/drain regions on second sides of the channel regions, bitlines extending in the first direction on the substrate and connected to corresponding ones of the first source/drain regions, respectively, data storage elements connected to the second source/drain regions, respectively, and capping films between the second source/drain regions and corresponding ones of the data storage elements, respectively, the capping filing including insertion holes, respectively, wherein at least portions of the second source/drain regions are inserted into corresponding ones of the insertion holes of the capping films, respectively.

A semiconductor device includes a channel including a two-dimensional semiconductor material, a source electrode and a drain electrode electrically connected to both ends of the channel, respectively, a two-dimensional material oxide layer on the channel, a dipole oxide layer on the two-dimensional material oxide layer, a dielectric layer on the dipole oxide layer, and a gate electrode on the dielectric layer.

A two-dimensional (2D) material growth substrate includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a strain control buffer layer formed on the second surface of the semiconductor substrate; a surface protective layer formed on the first surface of the semiconductor substrate; and a 2D material layer formed on the surface protective layer. The 2D material layer is configured to generate one of a tensile strain and a compressive strain. The semiconductor substrate and the strain control buffer layer include materials having different thermal expansion coefficients, and a combined thermal expansion coefficient of the semiconductor substrate and the strain control buffer layer is substantially similar to a thermal expansion coefficient of the 2D material layer.

Provided is a semiconductor device by which the integration level is improved, and specifically provided is a semiconductor device including a gate electrode extending lengthwise in a first direction, a plurality of channel layers that penetrate the gate electrode in a second direction intersecting the first direction, and are spaced apart in the first direction, and a gate insulating film including a plurality of gate insulating film patterns, each gate insulating film pattern at least partially covering a respective channel layer of the plurality of channel layers, wherein a height of each respective channel layer of the plurality of channel layers in a third direction intersecting with the first direction and the second direction is greater than a width of the respective channel layer of the plurality of channel layers in the first direction.