A method of forming a semiconductor device comprises the following steps. A dielectric layer is formed over a substrate. A 2D material layer is formed over the dielectric layer. An adhesion layer is formed over the 2D material layer. Source/drain electrodes are formed on opposite sides of the adhesion layer. A first high-k gate dielectric layer is formed over the adhesion layer, wherein the adhesion layer has a material different from a material of the first high-k gate dielectric layer.

A method of manufacturing a semiconductor layer includes preparing an insulating layer comprising a silicon oxide. A metal mask is formed on the insulating layer. An oxygen plasma process is performed on the metal mask. The metal mask is removed. The insulating layer is loaded into a chamber to form a semiconductor layer.

Semiconductor structures and methods of forming the same are provided. An exemplary semiconductor structure includes an isolation feature over a semiconductor substrate, a fin-shaped base protruding from the semiconductor substrate and through the isolation feature, first nanostructures vertically stacked above a top surface of the fin-shaped base, a middle dielectric layer disposed above the first nanostructures, a first barrier layer interfacing with a top surface of the middle dielectric layer, a second barrier layer interfacing with a bottom surface of the middle dielectric layer, second nanostructures vertically stacked above the middle dielectric layer, a bottom source/drain feature abutting at least one of the first nanostructures, a top source/drain feature abutting at least one of the second nanostructures, a bottom gate structure wrapping around at least one of the first nanostructures, and a top gate structure wrapping around at least one of the second nanostructures.

A method for manufacturing a semiconductor device includes: forming a two-dimensional material layer made of transition metal dichalcogenides on a semiconductor substrate unit; forming two lower metallic layers made of first metallic material and spaced apart on the two-dimensional material layer; forming two upper metallic layers made of second metallic material respectively on the two lower metallic layers so as to form two double-layer metal structures; and subjecting the two double-layer metal structures to a selective annealing process and cooling to room temperature. The semiconductor device made by the method is also provided.

A halide perovskite-based complementary semiconductor device according to an embodiment of the present invention includes a substrate, a two-dimensional material layer formed on an upper surface side of the substrate and including a hole injection layer and an electron injection layer, a halide perovskite layer formed on the two-dimensional material layer, and an electrode layer formed on the halide perovskite layer and including a drain electrode, an output electrode, and a source electrode.

The present invention relates to a single-crystalline Al.sub.2O.sub.3 dielectric compatible with two-dimensional materials and an integrated device thereof. A single-crystalline Al thin film is produced on a single-crystalline graphene/germanium (110) substrate via the van der Waals (vdW) epitaxy approach, the single-crystalline Al thin film is peeled off from the graphene/germanium substrate, and intercalative oxidation is performed to produce the single-crystalline Al.sub.2O.sub.3 dielectric compatible with two-dimensional materials on the lower surface of the single-crystalline Al thin film. The gate leakage current (J<110.sup.5 A cm.sup.2), interface state density (D.sub.it=8.410.sup.9 cm.sup.2 eV.sup.1), and dielectric strength (E.sub.bd=17.4 MV/cm) of the single-crystalline Al.sub.2O.sub.3 dielectric obtained in the present invention can meet the requirements of the international roadmap for devices and systems (IRDS) for low power consumption devices.

A semiconductor device and a method of fabricating the same are provided. The semiconductor device may include a source electrode, a drain electrode, an insulating region between the source electrode and the drain electrode, and a channel layer. The channel layer may be on the source electrode, the insulating region, and the drain electrode. The channel layer may include a source region on the source electrode, a drain region on the drain electrode, and a channel region on the insulating region. The source region and the drain region may include a precious metal element. The precious metal element in the drain region may be the same as the precious metal element in the source region. The channel region may include a first two-dimensional material layer having precious metal element-based semiconductor characteristics that may be the same as precious metal element-based semiconductor characteristics of the precious metal element.

A semiconductor device may include a first gate electrode and a second gate electrode spaced apart from each other on a substrate, a first channel layer on one side of the first gate electrode, a second channel layer on one side of the second gate electrode, and a third gate electrode connecting the first gate electrode and the second gate electrode to each other. The first channel layer and the second channel layer may extend in a first direction and the first direction may be perpendicular to the substrate.

A two-dimensional (2D) material growth substrate includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a strain control buffer layer formed on the second surface of the semiconductor substrate; a surface protective layer formed on the first surface of the semiconductor substrate; and a 2D material layer formed on the surface protective layer. The 2D material layer is configured to generate one of a tensile strain and a compressive strain. The semiconductor substrate and the strain control buffer layer include materials having different thermal expansion coefficients, and a combined thermal expansion coefficient of the semiconductor substrate and the strain control buffer layer is substantially similar to a thermal expansion coefficient of the 2D material layer.

Provided is a semiconductor device by which the integration level is improved, and specifically provided is a semiconductor device including a gate electrode extending lengthwise in a first direction, a plurality of channel layers that penetrate the gate electrode in a second direction intersecting the first direction, and are spaced apart in the first direction, and a gate insulating film including a plurality of gate insulating film patterns, each gate insulating film pattern at least partially covering a respective channel layer of the plurality of channel layers, wherein a height of each respective channel layer of the plurality of channel layers in a third direction intersecting with the first direction and the second direction is greater than a width of the respective channel layer of the plurality of channel layers in the first direction.