An SiC semiconductor device includes an SiC chip having a main surface, a channel region formed in a surface layer portion of the main surface, a drift region adjacent to the channel region in the surface layer portion of the main surface, a gate insulating film that is formed on the main surface and has a channel covering portion which covers the channel region and a drift covering portion which covers the drift region, a planar gate electrode that is arranged on the channel covering portion and opposes the channel region across the channel covering portion in a vertical direction, and a planar source electrode that is arranged on the drift covering portion at an interval from the planar gate electrode such as to oppose the planar gate electrode in a horizontal direction and opposes the drift region across the drift covering portion in the vertical direction.

A HEMT device comprises a trench-source contact which includes a first conductive portion and a second conductive portion superimposed on the first conductive portion. The first conductive portion is of a metal material which has a work function value lower than the work function value of the metal material of the second conductive portion.

A semiconductor device according to an embodiment includes: a semiconductor portion having a cell region and a terminal region provided outside the cell region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a front surface side of the semiconductor portion; a control electrode provided in the semiconductor portion via one of a plurality of first insulators arranged in a direction from the cell region to the terminal region; and a third electrode provided in the semiconductor portion via a second insulator between itself and the control electrode. A hollow portion is provided inside a terminal insulator, which is provided closer to the terminal region side than to the control electrode, among the plurality of first insulators.

A semiconductor structure includes a substrate, several gate structures formed in the substrate, dielectric portions formed on the respective gate structures, spacers adjacent to and extending along the sidewalls of the dielectric portions, source regions formed between the substrate and the spacers, and contact plugs formed between adjacent gate structures and contact the respective source regions. The source regions are adjacent to the gate structures. The sidewalls of the spacers are aligned with the sidewalls of the underlying source regions.

A semiconductor device includes an epitaxial layer on a substrate, a body region and a trench gate structure in the epitaxial layer, and a planar gate on the epitaxial layer. The trench gate structure is extended along a first direction and adjacent to the body region. The planar gate is extended along a second direction. The second direction and the first direction have a non-zero included angle therebetween. A portion of the planar gate is located directly above the body region. A source region is disposed in the body region. In a top view, a portion of the epitaxial layer is laterally separated from the body region, the trench gate structure, and the planar gate. The portion of the epitaxial layer and the source region are located on two opposite sides of the planar gate, respectively.

A semiconductor device including a semiconductor layer, a trench gate structure and a conductive layer is provided. The semiconductor layer has a first surface and a second surface. The trench gate structure is at least partially located in a trench on the first surface of the semiconductor layer. The semiconductor layer includes a source region, a body region and a drift region. The source region extends from the first surface toward the second surface, a plurality of recesses are disposed on the first surface, the conductive layer adjoins the first surface and extends into the plurality of recesses. The plurality of recesses are arranged in the first surface of the semiconductor layer, so that the conductive layer extends into the recess when adjoining the first surface, so as to increase a contact area between the conductive layer and the source region per unit area and reduce a source contact resistance.

A semiconductor device includes a foundation layer and a transistor layer. The foundation layer is based on single-crystalline silicon carbide and includes a current propagation region of a first conductivity type and a non-depletable shielding structure of a second conductivity type. The transistor layer is based on epitaxially grown single-crystalline silicon carbide and includes a transistor cell (TC) configured to control a current through the current propagation region. The transistor layer is formed on the foundation layer after formation of the shielding structure in the foundation layer such that an epitaxial interface forms between the transistor foundation layer and the layer. The current propagation region extends from the epitaxial interface between neighboring partial regions of the shielding structure. Along a vertical line orthogonal to the epitaxial interface and through a pn junction between the shielding structure and a region of the first conductivity type in the transistor layer, a net dopant concentration changes by at least 1e17 1/cm.sup.3 per 0.1 m at the position of the pn junction.

A method for producing a power semiconductor component includes: providing a power semiconductor partial structure having an insulating layer arranged on an upper side of a semiconductor body and a contact hole proceeding from an upper side of the insulating layer, extending at least partly within the insulating layer and configured for electrical contacting of a contact region below the upper side; at least partly covering the upper side and a surface of the contact hole with an adhesion promoter layer; at least partly covering the adhesion promoter layer with a tungsten-comprising layer having a first thickness dimensioned such that the tungsten-comprising layer fills the contact hole; removing part of the tungsten-comprising layer in a region of the upper side such that the tungsten-comprising layer has a second thickness in the upper side region that is less than the first thickness; and applying a connection layer to the tungsten-comprising layer.

A semiconductor component includes: a SiC semiconductor body; a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body, the trench having a conductive connection structure, a structure width at a bottom of the trench, and a dielectric layer covering sidewalls of the trench; a shielding region along the bottom and having a central section which has a lateral first width; and a contact formed between the conductive connection structure and the shielding region. The conductive connection structure is electrically connected to a source electrode. In at least one doping plane extending approximately parallel to the bottom, a dopant concentration in the central section deviates by not more than 10% from a maximum value of the dopant concentration in the shielding region in the doping plane. The first width is less than the structure width and is at least 30% of the structure width.

The present disclosure relates to a method for manufacturing a trench-gate MOSFET. In the method, a first trench is formed in a first region and a second trench is formed in a second region in an epitaxial layer. A first well is formed in a bottom surface of the first trench in the first region, and a body region is formed in the epitaxial layer in the second region, simultaneously in one ion implantation process with one mask being used. Thus, the method reduces a number of masks and simplifies ion implantation processes, thereby reducing manufacturing cost.