Methods, systems, and devices for front-to-front bonding in a stacked memory system are described. The stacked memory system may include a package substrate and a volatile memory die with a front side. The stacked memory system may also include a logic die with a front side that is bonded with the front side of the volatile memory die. The back side of the stacked memory system may be coupled with a conductive bump that in turn is coupled with the package substrate.

A memory device is provided. The memory device includes a first cell array stack including first gate electrodes, a first channel structure, and first pad portions respectively connected to the first gate electrodes and having a step shape, a second cell array stack disposed on the first cell array stack and including second gate electrodes, a second channel structure, and second pad portions respectively connected to the second gate electrodes and having a step shape, a first vertical contact passing through any one of the first pad portions and first extension portions below the any one of the first pad portions, a second vertical contact passing through any one of the second pad portions and second extension portions below the any one of the second pad portions, and a bonding pad between the first and second vertical contacts and electrically connected to the first and second vertical contacts.

A memory device is provided. The memory device includes a first cell array stack including first gate electrodes, a first channel structure, and first pad portions respectively connected to the first gate electrodes and having a step shape, a second cell array stack disposed on the first cell array stack and including second gate electrodes, a second channel structure, and second pad portions respectively connected to the second gate electrodes and having a step shape, a first vertical contact passing through any one of the first pad portions and first extension portions below the any one of the first pad portions, a second vertical contact passing through any one of the second pad portions and second extension portions below the any one of the second pad portions, and a bonding pad between the first and second vertical contacts and electrically connected to the first and second vertical contacts.

A chip structure includes an optical integrated circuit chip including a first waveguide extending in a horizontal direction and an optical guide unit, an electronic integrated circuit chip on the optical integrated circuit chip, and a connector above the optical integrated circuit chip and including a body, a second waveguide extending from an upper surface to a lower surface of the body, and an engagement groove extending inward from the upper surface of the body, wherein the first waveguide includes an edge coupler located at an end adjacent to the optical guide unit among both ends of the first waveguide, and the optical guide unit is configured to transfer signals between the first waveguide and the second waveguide.

A chip package includes a mother chip, a daughter chip, a molding compound, a first redistribution layer, and a second redistribution layer. The daughter chip is located on a first surface of the mother chip. The molding compound covers the mother chip and the daughter chip, and the daughter chip is surrounded by the molding compound. The first redistribution layer is located on the first surface of the mother chip and is covered by the molding compound. The second redistribution layer is electrically connected to the first redistribution layer, and is located on one of a second surface of the mother chip and a surface of the molding compound. One of the first redistribution layer and the second redistribution layer is electrically connected to the daughter chip, and the other is electrically connected to the mother chip.

A semiconductor package and a method for making the same are provided. The semiconductor package includes: a primary semiconductor die; an auxiliary semiconductor die attached onto a top surface of the primary semiconductor die; a first thermally conductive layer formed on a top surface of the auxiliary semiconductor die, wherein the first thermally conductive layer includes graphene-coated metallic particles; and a heat spreader thermally coupled with a top surface of the first thermally conductive layer.

A memory module may include a module substrate including first substrate pads and an insertion portion that has a module power terminal on a first substrate side portion of the module substrate; at least one semiconductor device on the module substrate and including chip pads electrically connected to the first substrate pads; substrate wirings including a first power connection wiring that electrically connects the module power terminal and the at least one semiconductor device; test wirings including a power test wiring that is branched from the first power connection wiring and has an end portion exposed from a second substrate side portion, the second substrate side portion adjacent the first substrate side portion; and a short protection structure on the module substrate, the short protection structure being adjacent the second substrate side portion, in the power test wiring, and configured to selectively block electrical flow through the power test wiring.

Provided is a glass circuit board and a manufacturing method thereof and an imaging device that achieve higher reliability. A glass circuit board including: a glass substrate serving as a core material including a first side, a second side located opposite from the first side, an outer end face located between the first side and the second side, and a through hole penetrating between the first side and the second side; an insulating first resin layer covering the first side; an insulating second resin layer covering the second side; a third resin layer that covers the inner surface of the through hole and is continuous with the first resin layer and the second resin layer; a fourth resin layer that covers the outer end face and is continuous with the first resin layer and the second resin layer; a first core wiring provided on the first side with the first resin layer interposed between the first core wiring and the first side; a second core wiring provided on the second side with the second resin layer interposed between the second core wiring and the second side; and a feed-through wiring provided on the inner surface of the through hole with the third resin layer interposed between the feed-through wiring and the inner surface.

A method for manufacturing a semiconductor package such as CoWoS-L, the method including: preparing an intermediate structure having a base material with a first main surface and a second main surface on the rear side of the first main surface, and a redistribution layer provided on the first main surface and having an insulating resin layer and wiring, the base material having a resin portion including a through portion that penetrates from the first main surface to the second main surface, and the redistribution layer forming a trench having a bottom surface on which the through portion is exposed; and cutting the through portion along the trench, thereby forming a plurality of wiring structures having base materials divided.

A semiconductor device assembly is disclosed. The semiconductor device assembly includes a semiconductor substrate having a plurality of die locations at which a plurality of semiconductor dies are implemented, a scribe area interleaved between the plurality of die locations, and a peripheral area near a periphery of the semiconductor substrate. A first passivation material is disposed at the plurality of die locations, and a second passivation material is disposed at the scribe area and the peripheral area. The first passivation material and the second passivation material implement a bonding surface of the semiconductor device assembly.