The present invention discloses a stacking system, which includes a system-on-wafer stacked on a photonic base, the photonic base provides a light transmission path, and a power base, which is configured above, below or beside the photon base, wherein the power base includes a power grid, a heat dissipation is stacked on the front of the system-on-wafer.

The present invention discloses a stacking system, which includes a system-on-wafer stacked on a photonic base, the photonic base provides a light transmission path, and a power base, which is configured above, below or beside the photon base, wherein the power base includes a power grid, a heat dissipation is stacked on the front of the system-on-wafer.

A semiconductor chip package includes a package substrate, at least one semiconductor chip, and a cold plate lid. The cold plate lid may be configured to cool the at least one semiconductor chip and minimize warpage of the package substrate. The cold plate lid may be bonded to the package substrate and thermally bonded to the rear surface of the at least one semiconductor chip. The cold plate lid further comprises an outer housing, a fluid inlet and a fluid outlet, and a flow plate. The outer housing may define an interior space and have a bottom surface bonded to the at least one semiconductor chip. The flow plate divides the interior space into an upper chamber and a lower chamber. Fluid flows from the upper chamber through apertures in the flow plate and into the lower chamber in a direction perpendicular to the rear surface of the semiconductor chip.

A semiconductor package includes a package substrate having first and second substrate pads thereon, a first semiconductor chip on the package substrate and including a first chip pad, a second semiconductor chip on the first semiconductor chip and including a second chip pad on a lower surface of the second semiconductor chip, a first bonding wire contacting the first substrate pad and the first chip pad, and a second bonding wire contacting the second substrate pad and the second chip pad. An uppermost portion of the second bonding wire is lower than or coplanar with the lower surface of the second semiconductor chip.

A microelectronic device includes a memory array structure, an additional memory array structure over and attached to the memory array structure, and a control circuitry structure over and attached to the additional memory array structure. The memory array structure includes an array region having memory cells. The additional memory array structure includes an additional array region having additional memory cells. The additional array region horizontally overlaps the array region. The control circuitry structure includes a control circuitry region horizontally overlapping each of the array region and the additional array region, and having control logic devices. The control logic devices are coupled to the memory cells and the additional memory cells. Gates of transistors of the control logic devices are positioned vertically closer to the additional memory cells than are channels of the transistors. Related methods and memory devices are also described.

A microelectronic device includes a memory array structure, an additional memory array structure over and attached to the memory array structure, and a control circuitry structure over and attached to the additional memory array structure. The memory array structure includes an array region having memory cells. The additional memory array structure includes an additional array region having additional memory cells. The additional array region horizontally overlaps the array region. The control circuitry structure includes a control circuitry region horizontally overlapping each of the array region and the additional array region, and having control logic devices. The control logic devices are coupled to the memory cells and the additional memory cells. Gates of transistors of the control logic devices are positioned vertically closer to the additional memory cells than are channels of the transistors. Related methods and memory devices are also described.

A microelectronic device includes a memory array structure, an additional memory array structure over and attached to the memory array structure, and a control circuitry structure over and attached to the additional memory array structure. The memory array structure includes an array region having memory cells. The additional memory array structure includes an additional array region having additional memory cells. The additional array region horizontally overlaps the array region. The control circuitry structure includes a control circuitry region horizontally overlapping each of the array region and the additional array region and having control logic devices. The control logic devices are coupled to the memory cells and the additional memory cells. Channels of transistors of the control logic devices are positioned vertically closer to the additional memory cells than are gates of the transistors. Related methods and memory devices are also described.

A microelectronic device includes a memory array structure, an additional memory array structure over and attached to the memory array structure, and a control circuitry structure over and attached to the additional memory array structure. The memory array structure includes an array region having memory cells. The additional memory array structure includes an additional array region having additional memory cells. The additional array region horizontally overlaps the array region. The control circuitry structure includes a control circuitry region horizontally overlapping each of the array region and the additional array region and having control logic devices. The control logic devices are coupled to the memory cells and the additional memory cells. Channels of transistors of the control logic devices are positioned vertically closer to the additional memory cells than are gates of the transistors. Related methods and memory devices are also described.

A method for forming a semiconductor device is provided. The method includes providing a base material block; forming a photoresist layer; forming ultraviolet-proof particles; patterning the photoresist layer through the ultraviolet-proof particles; etching the base material block through the patterned photoresist layer to form an array of vertical holes; filling in the array of vertical holes a thermally conductive material to form an array of thermally conductive vias, wherein the array of thermally conductive vias and the base material block constitute a thermally conductive block; providing a semiconductor die stack with a primary semiconductor die and an auxiliary semiconductor die, wherein the primary semiconductor die comprises a top surface having a first region and a second region besides the first region, wherein the auxiliary semiconductor die is attached onto the first region; attaching the thermally conductive block on the second region; and attaching a heat spreader.

The present disclosure provides a chip package structure and a fabrication method thereof, a memory system, and an electronic apparatus, and relates to the field of chip package technology. The chip package structure includes a stack structure and at least one first conductive pillar. The stack structure includes a plurality of semiconductor structures that are stacked. The stack structure includes a first surface and a second surface that are opposite in a stacking direction. The first conductive pillar extends along the stacking direction from the first surface of the stack structure, penetrates through at least one of the semiconductor structures, and is connected to one of the semiconductor structures. The above-mentioned chip package structure may be applied in a memory system to realize read and write operations of data.