A computer-implemented method for simulation of an integrated circuit for yield analysis includes: a) for plurality of variables, generating initial sampling sets by sampling from provided distributions related to physical properties of circuits; b) selecting at least one sample from each initial set randomly and combining into initial simulation set; c) running initial simulation of operation of circuit, applying initial simulation set, the operation having passing/failing criterion; d) if fails: storing samples of initial set into initial sampling distributions for each variable; e) repeating steps b)-d) until sufficient failures obtained; f) building importance sampling distribution based on each initial sampling distribution, the importance distribution having lower, center, upper portions; g) generating secondary simulation set by drawing samples from importance sampling distribution for each variable; h) simulating circuit by applying the secondary set; i) repeating steps g)-h); j) mapping resulting yields to provided distributions, to obtain a yield.

A method and a system for predicting a gas content in transformer oil based on a joint model are provided and belong a field of transformer failure prediction. The method includes the following: determining a type and a time series of gas to be predicted related to a failure, processing an original series by adopting empirical mode decomposition (EMD) and local mean decomposition (LMD) for a non-stationarity characteristic of a dissolved gas concentration series in oil; performing normalization on each sub-series component, dividing a training sample and a test sample; and establishing a deep belief network (DBN) prediction model for each of the sub-series components for training, performing superposition and reconstruction on the established DBN prediction model to perform characteristic extraction and classification on multi-dimensional data of the failure, evaluating prediction performance of the prediction model through calculating an error index.

Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

In order to predict the future evolution of a health-state of an equipment and/or a processing unit of a chemical production plant, e.g., a steam cracker, a computer-implemented method is provided, which builds a data-driven model for the future key performance indicator based on the key performance indicator of today, the processing condition of today, and the processing condition over a prediction horizon.

A network construction support system (100) generates one or more pieces of layout data (101) indicating a layout of construction assisting tools (140). The network construction support system calculates a countermeasure cost and an estimated risk amount, for each layout data, the countermeasure cost increasing as a number of units of construction assisting tools increases, the estimated risk amount decreasing as the number of units of construction assisting tools increases and as a narrowed range by each construction assisting tool narrows. The network construction support system judges an appropriateness of the layout data for the apparatus network system, for each layout data, on the basis of a countermeasure cost, an estimated risk amount, and an allowable risk amount which is allowed for the apparatus network system, The network construction support system outputs layout data judged to be appropriate for the apparatus network system.

The invention provides a yield rate prediction method for manufacture of integrated circuit wafers, which includes the following steps: obtaining candidate reference product models; obtaining parameters of the candidate reference products; obtaining functions of candidate reference products; predicting candidate reference products; selecting a final reference product; obtaining a new product prediction model; and predicting yield rate of new product. The yield rate prediction method for manufacture of integrated circuit wafer provided by the disclosure is performed based on the functional relationship between random defect density and yield rate in wafer manufacturing. By referring to the yield rate data of mature products on the production line, establishing data model and performing regression analysis, a more accurate yield rate prediction value of a new product can be obtained, thus providing a new product yield rate prediction method for manufacture of semiconductor integrated circuit wafers.