A laminated structure includes an amorphous substrate having an insulating surface, an orientation pattern on the amorphous substrate, an insulating layer in contact with a side surface of the orientation pattern and surrounding the periphery of the orientation pattern, and a semiconductor pattern containing gallium nitride on the orientation pattern, wherein the insulating layer has a first region overlapping the semiconductor pattern and a second region not overlapping the semiconductor pattern.

In accordance with various embodiments of the present disclosure, a semiconductor device is provided. In some embodiments, the semiconductor device comprises a substrate made of a semiconductor material, a gate structure placed on the substrate, a passivation layer placed on the substrate and on a portion of the gate structure, a sealing oxide layer placed on the passivation layer, a first field plate placed on a portion of the sealing oxide layer, a dielectric layer placed on the first field plate and on the sealing oxide layer, a second field plate placed on a portion of the layer, and a source contact metallization and a drain contact metallization. The sealing oxide layer is thicker than the passivation layer.

There is provided a method for manufacturing a nitride stack, including: (a) preparing a substrate having at least a surface layer portion composed of a first group III nitride, the substrate being unloaded from a depositing apparatus in which the first group III nitride has been grown; (b) subjecting the substrate to a predetermined oxidation treatment using an oxidation treatment device to convert an outermost layer of the first group III nitride into a protective layer composed of a group III oxide; (c) loading the substrate into a predetermined processing chamber and heating the substrate in a reducing atmosphere to remove the protective layer from a surface of the substrate; and (d) growing a second group III nitride on a surface of the first group III nitride exposed by removing the protective layer, without unloading the substrate from the processing chamber.

An example field effect transistor includes a substrate, a first source metal over the substrate, a second source metal over the substrate, and a drain metal positioned between the first source metal and the second source metal over a channel of the field effect transistor. The drain metal includes a drain metal body having a notched region between the first source metal and the second source metal over the channel, and the notched region defines a first projecting portion and a second projecting portion of the drain metal body. In one aspect, the first projecting portion and the second projecting portion are positioned on respective sides of the notched region. The notched region is a triangular-shaped notched region in one example.

The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a gate electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.

A semiconductor package includes a semiconductor chip, a heat radiating member on which the semiconductor chip is mounted, and a sealing member sealing the semiconductor chip. The sealing member is made of a liquid crystal polymer.

The present invention relates to a method for manufacturing a group 3 nitride semiconductor template and a semiconductor template manufactured thereby, wherein a laser lift-off technique and a chemical lift-off technique are used so that a high-quality group 3 nitride semiconductor layer can be formed on the top of a high heat dissipation support substrate having the same or a similar lattice constant and thermal expansion coefficient.

A semiconductor device includes multiple GaN units arranged separately from each other in a first direction in a first encapsulation resin. The GaN unit includes a substrate, a GaN transistor arranged at a substrate front surface side of the substrate, and a post arranged on a source pad, a drain pad, and a gate pad of the GaN transistor and exposed from the first encapsulation resin. The post includes a source post formed on the source pad in one of two adjacent ones of the GaN units in the first direction, and a drain post formed on the drain pad in the other one of the two adjacent ones of the GaN units in the first direction. The semiconductor device includes an interconnect layer arranged on an encapsulation front surface and electrically connects the source post and the drain post.

The packaging structure of the high electron mobility transistor includes a first terminal, a second terminal, a semiconductor die and a packaging body. The first terminal includes a first platform, a first connection part and multiple first pins. The second terminal includes a second platform, a second connection part and multiple second pins. The semiconductor die includes first electrode and second electrode. The first electrode is coupled to first platform and the second electrode is coupled to second platform. The packaging body encapsulates the semiconductor die, the first platform and the second platform. The first connection part has a first exposed side surface, the second connection part has a second exposed side surface, the first exposed side surface and the second exposed side surface are located outside the package, the first exposed side surface and the second exposed side surface have a first distance D1>2.5 mm.