A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

A method of fabricating a semiconductor device may include providing a substrate, forming active fin regions, source/drain patterns, gate structures, and an inter-gate insulating layer on the substrate, forming full height contacts, forming full height gate contacts, recessing a first subset of the full height contacts and a second subset of the full height gate contacts to form reduced height contacts and reduced height gate contacts, respectively, forming an upper insulating pattern, and forming interconnection patterns on the full height contacts, the full height gate contacts, and the upper insulating pattern.

An integrated circuit including a first standard cell placed continuously on a row having a first height and a row having a second height different from the first height. The integrated circuit also includes a second standard cell continuously placed on a row having the first height and a row having the second height, a plurality of first power lines formed on boundaries of the plurality of rows and configured to supply a first supply voltage to the standard cells, and a plurality of second power lines formed on boundaries of the plurality of rows and configured to supply a second supply voltage to the standard cells. A placement sequence of the power lines supplying a voltage to the first standard cell being different from a placement sequence of the power lines supplying a voltage to the second standard cell.