Disclosed in the present application are a silicon carbide MOSFET device and a manufacturing method therefor. The silicon carbide MOSFET is provided with a first withstand voltage masking structure and a second withstand voltage masking structure. The withstand voltage performance of the device is improved, the breakdown problem of a gate insulating dielectric layer can be avoided, the electrostatic effect of the device on a severe environment and the high-voltage peak tolerance capability in the circuit are improved, and the surge voltage resistance of the device and the over-voltage protection capability are improved. Ion implantation can be carried out on a first trench to form the first withstand voltage masking structure, and ion implantation can be carried out on a second trench to form the second withstand voltage masking structure.

An electronic device can include a buried shield and at least one gap region. In an implementation, a source region can include shallow and deep portions. A centerline through the gap region may pass through the shallow portion and not the deep portion. In the same or different implementation, the shallow portion can overlap the gap region, and the deep portion does not overlap the gap region. The electronic device can be designed to have a good balance between source contact resistance and BV.sub.DS. In a further implementation, the electronic device can include first and second gap regions. Lengths of the first and second gap regions can lie long lines that interest each other. The gap regions can be designed so that a gap region resistance may be within an order of magnitude of a channel resistance corresponding to channel regions of transistor structures within a power transistor.

An electronic device can include a buried shield and a gap region. The electronic device can include a body contact region, a deep body region, or both. The deep body region can be spaced apart from the gap region and not cause R.sub.SP to decrease. A combination of the body contact region and the deep body region can form a terraced conductive structure to couple the buried shield and a source terminal to each other. In an implementation, the body contact region, the deep body region, or another p-type doped region can be spaced apart from a gate member by at least a minimum distance to improve long-term reliability of a gate dielectric layer. The minimum distance can be applied as a design rule when designing the electronic device.

A semiconductor component, in particular a transistor, which is based on gallium nitride. The semiconductor component includes: a substrate layer and/or drain layer, a first-type-doped drift layer, a channel layer, which is second-type-doped, and a first-type-doped source layer, wherein the channel layer is arranged in the vertical direction between the source layer and the drift layer. The semiconductor component has a gate trench, which extends in the vertical direction from the source layer to the drift layer and is adjacent to the channel layer and at least a portion of the source layer. The semiconductor component has one or more second-type-doped shielding regions, each of which is located at least partially in the vertical direction below the gate trench and at least partially within the drift layer, wherein one or the plurality of shielding regions are diffused. A method for producing a semiconductor component is also described.

A super junction IGBT device based on a controlled hole extraction structure and a manufacturing method thereof are provided. The super junction IGBT device includes an epitaxial layer. P-type columns and N-type columns are periodically disposed in the epitaxial layer. P-type base regions are disposed above the N-type columns. The P-type base regions include first P-type base regions disposed in a rectangular array. The P-type columns include first P-type columns and second P-type columns. The first P-type columns are connected to the first P-type base regions by the controlled hole extraction structure. When the super junction IGBT device is turned off, the controlled hole extraction structure form a hole extraction channel between the first P-type columns and the first P-type base regions, thereby accelerating a turn-off speed by extracting holes.

In a method for manufacturing a semiconductor device having a semiconductor layer formed with a super junction structure in which an n-type column and a p-type column are alternately and repeatedly arranged at least in one direction, the super junction structure is formed in the semiconductor layer based on a pattern deviation of a shielding layer formed on a surface of the semiconductor layer relative to a design pattern, the shielding layer having an opening corresponding to at least one of an n-type column formation range where the n-type column is to be formed or a p-type column formation range where the p-type column is to be formed.

An SiC semiconductor device includes an SiC layer that includes a main surface, a trench structure that is formed in the main surface and extends in a first extension direction in plan view, and a gate structure of a planar electrode type that is arranged on the main surface and extends in a second extension direction other than the first extension direction in plan view.

An SiC semiconductor device includes a first SiC layer, a second SiC layer laminated on the first SiC layer, a first impurity region of a p-type formed in the first SiC layer, a second impurity region of the p-type formed in the second SiC layer, first inversion columns of an n-type that are formed at an interval in the first SiC layer such as to invert a conductivity type of the first impurity region; and second inversion columns of the n-type that are formed at an interval in the second SiC layer such as to invert a conductivity type of the second impurity region.

The semiconductor device includes a chip having side surface, and an ornamental pattern formed in the side surface. The chip includes a semiconductor layer of a first conductivity type, and the ornamental pattern includes a mark of a second conductivity type that is formed in a portion constituted of the semiconductor layer in the side surface. The side surface includes a first side surface extending in a first direction in plan view and a second side surface extending in a second direction intersecting the first direction in plan view, and the ornamental pattern includes at least one of mark formed in one or both of the first side surface and the second side surface.

An SiC semiconductor device includes a first SiC layer of a first conductivity type that has a first axis channel oriented along a lamination direction, a second SiC layer of the first conductivity type that has a second axis channel oriented along the lamination direction and is laminated on the first SiC layer, a first region of a second conductivity type that extends along the first axis channel in the first SiC layer in cross-sectional view and extends in a first extension direction in plan view, and a second region of the second conductivity type that extends along the second axis channel in the second SiC layer in cross-sectional view and extends in a second extension direction intersecting the first extension direction such as to intersect the first region in plan view.