An SiC semiconductor device includes an SiC layer that includes a main surface and has an axis channel in a lamination direction, an impurity region of a p-type formed in the SiC layer, a trench that is formed shallower than the impurity region in the main surface and defines a lower region including a part of the impurity region between a bottom portion of the SiC layer and the trench, and an inversion column of an n-type that is formed in the lower region such as to extend along the axis channel and that inverts a conductivity type of the impurity region.

An SiC semiconductor device includes an SiC layer of a first conductivity type that includes a main surface and has an axis channel in a lamination direction, a trench that is formed in the main surface and demarcates a lower region between the trench and a bottom portion of the SiC layer, and a column region of a second conductivity type that is formed in the lower region inside the SiC layer and extends along the axis channel.

An SiC semiconductor device includes a first SiC layer of a first conductivity type which has a first axis channel oriented along a lamination direction, a second SiC layer of the first conductivity type which has a second axis channel oriented along the lamination direction and is laminated on the first SiC layer, a first region of a second conductivity type which extends along the first axis channel in the first SiC layer, and a second region of the second conductivity type which extends along the second axis channel in the second SiC layer and overlaps the first region in the lamination direction.

An SiC semiconductor device includes an SiC layer of a first conductivity type that has a main surface, an active region set in an inner portion of the main surface, an outer peripheral region set in a peripheral edge portion of the main surface, and a column region of a second conductivity type that is formed in the SiC layer at an interval in a horizontal direction along the main surface and includes impurity regions positioned in both the active region and the outer peripheral region.

A semiconductor device is provided, which comprises: a die layer; a trench extending into the die layer, wherein the trench comprises a trench bottom and trench side walls; a first dopant implantation region arranged below the trench bottom; a second dopant implantation region arranged below the first dopant implantation region; a first dopant diffusion layer extending laterally of the first dopant implantation region; and a second dopant diffusion layer extending laterally of the second dopant implantation region; wherein an extension of the second dopant diffusion region in the lateral direction matches an extension of the first dopant diffusion layer in the lateral direction.

Disclosed are a superjunction semiconductor device and a method of manufacturing the same. More particularly, a superjunction semiconductor device and a method of manufacturing the same include an additional structure that enables smooth current flow in a transition region and/or a ring region of the device, where the current concentrates locally during turn-on/turn-off operations of the device due to insufficient current paths compared to the cell region of the device, thereby improving reverse recovery characteristics and preventing device destruction.

The present disclosure provides an LDMOS device and a preparation method thereof, including: providing a substrate including a first drift region of a first conductivity type and a body region of a second conductivity type; forming a first gate structure and a first blocking structure, where the first gate structure is formed above a portion of the body region and a portion of the first drift region, the body region and the first drift region respectively include first and second regions not covered by the first gate structure, and the first blocking structure is formed above the second region; performing an ion implantation process, where a part of ions are implanted into the first region of the body region to form a body region contact region, and a part of ions are implanted into the second region after passing through the first blocking structure to form a first doped region.

A semiconductor device comprising an n-type epitaxial layer, a plurality of p-type column regions formed in the epitaxial layer so as to be spaced apart from each other in a plan view, and a gate electrode formed between each of the plurality of p-type column regions. The plurality of p-type column region is formed in the epitaxial layer and is composed of first, second and third sub-column regions, which are arranged in order from the side closer to a main surface of the epitaxial layer EP. Additionally, a distance between a position of a maximum impurity concentration of the first sub-column region and a position of a maximum impurity concentration of the second sub-column region is smaller than a distance between the position of the maximum impurity concentration of the second sub-column region and a position of a maximum impurity concentration of the third sub-column region.

The present disclosure relates a semiconductor device using a super junction structure, and includes: a semiconductor base body of a first conductivity type; a pillar part including a plurality of first pillars of a first conductivity type and a plurality of second pillars of a second conductivity type provided on the semiconductor base body to protrude in a thickness direction of the semiconductor base body; a pillar surrounding part of a first conductivity type or a second conductivity type provided around the pillar part; and a semiconductor element in which the pillar part is provided as an active region, wherein the plurality of first and second pillars have a striped shape in a plan view, and are alternately arranged in parallel to each other in a pillar width direction perpendicular to a longitudinal direction of each of the pillars.

A semiconductor device, including: a silicon carbide semiconductor substrate; a first semiconductor layer provided on the semiconductor substrate; a second semiconductor layer provided on the first semiconductor layer; first and second semiconductor regions selectively provided in the second semiconductor layer; a plurality of trenches penetrating through the first semiconductor regions and the second semiconductor layer; a plurality of gate electrodes respectively provided in the trenches via gate insulating films; a plurality of high-concentration regions provided in the first semiconductor layer, respectively facing the trenches in a depth direction; a plurality of connecting regions provided in the first semiconductor layer, contacting the high-concentration regions and the second semiconductor layer; a plurality of first electrodes provided on the first and second semiconductor regions; and a second electrode provided on the semiconductor substrate. Both the second semiconductor regions and the connecting regions are periodically disposed in a longitudinal direction of the trenches.