A p-type impurity concentration in a p-type trench underlayer is appropriately adjusted. A method for producing a field effect transistor includes: a body layer formation step of forming a p-type body layer by ion-implanting a p-type impurity; a trench formation step of forming a trench in an upper surface of a semiconductor substrate; a p-type trench underlayer formation step of forming the p-type trench underlayer below the trench by implanting a p-type impurity into a bottom surface of the trench while the upper surface of the semiconductor substrate is covered with an ion implantation mask; and a gate electrode formation step of forming a gate insulating film and a gate electrode in the trench. In the p-type trench underlayer formation step, the p-type impurity is implanted at a higher concentration than in the body layer formation step.

A superjunction device and a method for producing a superjunction device are disclosed. The superjunction device includes a semiconductor body including an inner region and an edge region laterally surrounding the inner region; a superjunction region comprising first regions of an effective first doping type and second regions of an effective second doping type arranged alternatingly in a first lateral direction of the semiconductor body. The first regions, in the inner region, have a first width and are spaced apart from each other at a first distance, in the edge region, have a second width and are spaced apart from each other at a second distance, and, in the inner region and the edge region, are elongated in a second lateral direction different from the first lateral direction. The second width is smaller than the first width and the second distance is smaller than the first distance.

The present invention involves a power device and a manufacturing method thereof. The method comprising steps of providing a semiconductor substrate, growing an epitaxial layer on the semiconductor substrate, forming an insulating layer on the epitaxial layer, forming a metal mask layer on the insulating layer, and performing an ion implantation process from above the metal mask layer on the epitaxial layer. The metal mask layer includes an ion implantation blocking region and an ion implantation penetration region.

A MOS transistor has a gate insulating film and a gate electrode disposed in a trench. A semiconductor substrate has: a bottom p-type layer in contact with the gate insulating film at a bottom surface of the trench; an intermediate n-type layer disposed within an interval between the bottom p-type layers; and a superjunction layer disposed below the bottom p-type layer. A p-type column layer of the superjunction layer is in contact with the intermediate n-type layer from a lower side. An n-type column layer of the superjunction layer is in contact with the bottom p-type layer and the intermediate n-type layers on both sides of the bottom p-type layer from a lower side.

A silicon carbide semiconductor device has a cell region that includes a main cell region, a sense cell region, and an element isolation region electrically separating the main cell region and the sense cell region. The element isolation region includes a plurality of isolation trenches and a plurality of isolation deep layers of a second conductivity type. The isolation trenches are disposed between the main cell region and the sense cell region, and extend deeper than a base layer to separate the base layer into a section adjacent to the main cell region and a section adjacent to the sense cell region. The isolation deep layers are respectively disposed at bottom portions of the isolation trenches in contact with bottom surfaces of the isolation trenches.

A semiconductor device includes: first pillar regions of a second conductivity type each formed on a lower side of the plurality of gate trenches into which a gate electrode is embedded; and a second pillar region of a first conductivity type formed between the first pillar regions adjacent to each other and having a higher impurity peak concentration than the drift layer. The second pillar region is made of a high concentration region and a low concentration region provided to at one lateral part of the second pillar region and having a lower impurity peak concentration than the high concentration region.

A semiconductor device includes a semiconductor substrate having a mesa structure, a dielectric layer surrounding the mesa structure, and a gate electrode over the dielectric layer. The semiconductor substrate includes a bottom source region, a contact source region, and a sidewall body region in the mesa structure. The semiconductor substrate includes a liner doped region adjoining a frontside surface of the semiconductor substrate and a drain region adjoining a backside surface of the semiconductor substrate. The bottom source region, the contact source region, and the drain region have a first conductivity type, and the sidewall body region and the liner doped region have a second conductivity type opposite to the first conductivity type. A bottom of the gate electrode is higher than a top end of a first portion of the liner doped region in the mesa structure.

The present disclosure provides an LDMOS device and a preparation method thereof, including: providing a substrate including a first drift region of a first conductivity type and a body region of a second conductivity type; forming a first gate structure and a first blocking structure, where the first gate structure is formed above a portion of the body region and a portion of the first drift region, the body region and the first drift region respectively include first and second regions not covered by the first gate structure, and the first blocking structure is formed above the second region; performing an ion implantation process, where a part of ions are implanted into the first region of the body region to form a body region contact region, and a part of ions are implanted into the second region after passing through the first blocking structure to form a first doped region.

A manufacturing method of a semiconductor device includes forming an interposed film above a second conductivity type semiconductor layer, forming a shielding film containing metal above the interposed film, forming openings that penetrate through the shielding film, and forming first conductivity type columns and second conductivity type columns alternately and repeatedly arranged along at least one direction by implanting first conductivity type impurity ions into the second conductivity type semiconductor layer through the openings.

A semiconductor device includes chip having a main surface, a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface, a gate structure of a trench type formed in the main surface and positioned in the semiconductor region, a body region of a second conductivity type formed in a region at a side of the main surface with respect to a depth position of a bottom wall of the gate structure in the surface layer portion of the main surface, and a high concentration region of the first conductivity type formed in a thickness range between the bottom wall of the gate structure and a bottom portion of the body region in the chip and having an impurity concentration higher than an impurity concentration of the semiconductor region.