An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.

A method includes forming a multilayer stack, which includes a plurality of semiconductor nanostructures and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are located alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, performing a doping process to dope a first dopant into the lateral recesses, forming inner spacers in the lateral recesses, performing an anneal process to diffuse the first dopant into the inner spacers, and forming a source/drain region contacting the inner spacers, wherein the source/drain region is electrically coupled to the plurality of semiconductor nanostructures.

Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin over a substrate, wherein the fin comprises first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming a sacrificial gate structure over the fin, removing portions of the fin not covered by the sacrificial gate structure, replacing the second semiconductor layers with a sacrificial dielectric material, recessing edge portions of the sacrificial dielectric material to form cavities between the first semiconductor layers, forming a dielectric spacer in the cavities by depositing a conformal layer of a dielectric liner layer on exposed surfaces of each cavity, forming source/drain features on opposite sides of the sacrificial gate structure, and replacing the sacrificial gate structure and the sacrificial dielectric material with a gate structure wrapping around the first semiconductor layers.

A semiconductor device structure and methods of forming the same are described. The method includes forming a fin structure over a substrate and depositing one or more spacers on a portion of the fin structure. The one or more spacers are deposited on sidewalls of the fin structure. The method further includes removing a first portion of the one or more spacers to expose the fin structure and recessing the fin structure. A first byproduct layer is formed on a second portion of the one or more spacers. The method further includes passivating the first byproduct layer, softening the first byproduct layer, removing a portion of the first byproduct layer to expose the recessed fin structure, and further recessing the fin structure.

The present disclosure provides a method that includes forming a stack including first and second semiconductor layers over a substrate, wherein the first and second semiconductor layers have different compositions and alternate with one another; patterning the stack to form active regions; forming an isolation structure to surround the active regions; forming a hard mask on the isolation structure; forming a dummy gate structure over the stack; recessing source/drain regions of the stack, resulting in source/drain trenches; selectively removing the second semiconductor layers, resulting in first gaps among the first semiconductor layers; forming dielectric interposers in the first gaps; performing a first etching process to laterally recess the dielectric interposers, resulting in second gaps; forming inner spacers in the second gaps; forming source/drain features in the source/drain trenches; removing the dummy gate structure; and removing a subset of the dielectric interposers while bottommost dielectric interposers remain.