Methods, systems, and apparatus for combined or separate implementation of coarse-to-fine neural architecture search (NAS), two-phase block NAS, variable hardware prediction, and differential hardware design are provided and described. A variable predictor is trained, as described herein. Then, a controller or policy may be used to iteratively modify a neural network architecture along dimensions formed by neural network architecture parameters. The modification is applied to blocks (e.g., subnetworks) within the neural network architecture. In each iteration, the remainder of the neural network architecture parameters are modified and learned with a differential NAS method. The training process is performed with two-phase block NAS and incorporates a variable hardware predictor to predict power, performance, and area (PPA) parameters. The hardware parameters may be learned as well using the variable hardware predictor.

Disclosed is a flip-flop unit design method comprising: analyzing signal delay of a clock control signal in a digital circuit; selecting a clock gating circuit among a plurality of types of clock gating circuits according to the signal delay, and coupling at least one edge-triggered flip-flop and the selected clock gating circuit to be a flip-flop unit, wherein the plurality of types of clock gating circuits enable or disable a first clock signal according to the clock control signal to generate a second clock signal, and the edge-triggered flip-flop transmits data at an edge of the second clock signal. The design method eliminates the glitch in the clock signal generated by the clock gating circuit, reduces the number of logic devices of the clock gating circuit, reduces the power consumption of the clock gating circuit. The design method is applicable to a flip-flop group with any number of edge-triggered flip-flops.