Disclosed is a vertical structure transistor element including a spacer layer made of an insulating material and a thickness-dependent material layer made of a thickness-dependent material that is a material having electrical conductivity changed according to a thickness and stacked on an upper end surface of the spacer layer, wherein the thickness-dependent material layer includes a first electrode area layer stacked on a first upper end surface, a second electrode area layer stacked on a second upper end surface, and a channel area layer stacked on a third upper end surface, and a thickness of the channel area layer is smaller than a thickness of the first electrode area layer and a thickness of the second electrode area layer.

A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is positioned above the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is positioned above the first insulating layer. The semiconductor layer is in contact with the second conductive layer and a side surface of the first insulating layer and a top surface of the first conductive layer in the first opening. The third insulating layer is in contact with a top surface of the first insulating layer and the semiconductor layer in the first opening. The second insulating layer is positioned above the third insulating layer and includes a second opening reaching the third insulating layer in a position overlapping the first opening. The third conductive layer is provided to fill the second opening and the first opening.

A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. In the semiconductor device, an insulating layer functioning as a first spacer is provided between a lower electrode that is one of a source electrode and a drain electrode of a transistor and an upper electrode that is the other, and an insulating layer functioning as a second spacer is provided over the upper electrode. The first spacer, the upper electrode, and the second spacer are provided with a first opening portion reaching the lower electrode. Inside the first opening portion, a semiconductor layer where a channel is formed is provided to connect the lower electrode and the upper electrode. Inside the first opening portion, a gate insulating layer and a gate electrode are provided to overlap with the semiconductor layer. An interlayer insulating layer including a second opening portion reaching the gate electrode is provided over the second spacer, the semiconductor layer, the gate insulating layer, and the gate electrode. The gate electrode includes a region in contact with a wiring over the interlayer insulating layer inside the second opening portion.

A semiconductor device including a semiconductor substrate, a lower metal contact disposed upon the semiconductor substrate, a gate structure disposed upon the lower metal contact, an upper metal contact disposed upon the gate structure, and a plurality of semiconductor carriers disposed in contact with both the lower metal contact and the upper metal contact, the plurality of semiconductor carriers disposed in channels passing through the gate structure.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first conductor, a first insulator, a second conductor over the first insulator, an oxide semiconductor, a second insulator, a third conductor, a third insulator, and a fourth insulator. In the semiconductor device, an opening portion reaching the first conductor is provided in the first insulator and the second conductor, part of the oxide semiconductor is placed in the opening portion and is in contact with a top surface of the first conductor, another part of the oxide semiconductor is placed over the opening portion and is in contact with at least part of a top surface of the second conductor, the second insulator is placed over the oxide semiconductor so as to be at least partly positioned in the opening, the third conductor is placed over the second insulator so as to be at least partly positioned in the opening, the third insulator is placed between a sidewall of the opening portion and the oxide semiconductor so as to be positioned in the opening, and the fourth insulator is placed between the sidewall of the opening portion and the third insulator, the third insulator comprises a metal oxide, and the fourth insulator comprises silicon nitride.

A semiconductor device that occupies a small area is provided. The semiconductor device includes an oxide semiconductor layer, first to third conductive layers, a first insulating layer, and a second insulating layer. The first conductive layer includes a first metal layer and a first metal oxide layer including the same metal as each other. The first metal layer is electrically connected to the oxide semiconductor layer through the first metal oxide layer. The second conductive layer includes a second metal layer and a second metal oxide layer including the same metal as each other. The second metal layer is electrically connected to the oxide semiconductor layer through the second metal oxide layer. The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first insulating layer. The oxide semiconductor layer is in contact with the top surface of the first metal oxide layer, the top surface and a side surface of the second metal oxide layer, and a side surface of the first insulating layer. The second insulating layer is positioned over the oxide semiconductor layer. The third conductive layer is positioned over the second insulating layer and overlaps with the oxide semiconductor layer with the second insulating layer therebetween.

The present disclosure discloses a semiconductor device and a preparation method thereof. The preparation method includes: providing a semiconductor structure including a first insulating layer, a source layer on the first insulating layer, and a second insulating layer on the source layer; forming multiple drain portions embedded and arranged in an array on an upper portion of the second insulating layer; etching the second insulating layer by using multiple drain portions as masks until the source layer is exposed, to form multiple columnar bodies arranged in an array on an upper surface of the source layer, the columnar bodies including insulating columns on the source layer and drain portions on the insulating columns; forming a channel material layer surrounding the columnar bodies in a circumferential direction; and forming a gate dielectric layer and a gate structure on one side of the channel material layer away from the columnar bodies.

A capacitor with large capacitance, a transistor with excellent electrical characteristics, a transistor with high on-state current, or a transistor with small parasitic capacitance is provided. A device includes a first insulating layer, a first conductive layer over the first insulating layer, a second insulating layer over the first insulating layer and the first conductive layer, and a capacitor over the first conductive layer. The second insulating layer includes an opening portion that reaches the first conductive layer and includes a narrowed upper portion. A lower electrode, an upper electrode, and a dielectric of the capacitor each include a portion positioned in the opening portion. The lower electrode includes a portion in contact with the top surface of the first conductive layer and a portion provided along the opening portion.