A semiconductor device includes a drift region of a first conductivity type that is formed in an interior of a chip and a plurality of FLRs that are formed in a surface layer portion of a first principal surface in an outer peripheral region such as to surround an active region, each FLR has FLR curve portions, each being of a curve shape in plan view shape, in four corner portions, each FLR has FLR rectilinear portions, each being of a rectilinear shape in plan view shape, between the four corner portions, and each FLR curve portion has a double-diffused structure including a first diffusion region at an inner side and a second diffusion region at an outer side that is lower in impurity concentration of a second conductivity type than the first diffusion region.

An object of the present disclosure is to suppress carrier injection in a termination region even with a malfunction in a back gate operation, in a semiconductor device with a double-sided gate structure. A semiconductor device with the double-sided gate structure includes: a buffer layer of a first conductivity type on a back surface of a drift layer; and a collector layer of a second conductivity type between the buffer layer and a collector electrode in an element region. A termination region does not include the collector layer between the collector electrode and the buffer layer, or the termination region includes the collector layer between the collector electrode and the buffer layer such that the collector layer in the termination region is less in total impurity quantity of the second conductivity type per unit area than the collector layer in the element region.

The semiconductor device includes: an active portion, a termination region that surrounds the active portion in a plan view, a drift layer of a first conductivity type that is provided over the active portion and the termination region, a base region of a second conductivity type that is provided on an upper surface side of the drift layer at the active portion, and a well region of the second conductivity type that is provided on the upper surface side of the drift layer at the termination region and that surrounds the base region in the plan view, in which the well region has a recess portion on a lower side, and a dimension of the recess portion in a depth direction is or more and or less of a dimension of the well region in the depth direction.

A semiconductor device comprises a semiconductor layer structure, a gate pad on the semiconductor layer structure, and a metal gate runner on the semiconductor layer structure. The metal gate runner comprises an inner gate runner that comprises a first inner segment and a second inner segment that interconnect at a first oblique angle.

A lateral silicon carbide power semiconductor device is disclosed. The device comprises a substrate and a silicon carbide semiconductor structure disposed on the substrate and having a principal surface. The semiconductor structure comprises a layer of first conductivity type disposed on the substrate, and a layer-shaped drift region of a second conductivity type, which is opposite to the first conductivity type, disposed directly on the layer so as to form an interface between the layer and the drift region. The drift region runs laterally along the principal surface between first and second ends. Doping in the drift region and the layer are arranged so as to deplete the drift region. The device comprises a first contact region to the drift region. The device comprises a second contact region to the second end of the drift region which is highly doped, which is of the first or second conductivity type which adjoins the second end of the drift region, is disposed in the drift region or in a region which adjoins the second end of the drift region The device comprises a highly-doped region of the first conductivity type extending into the semiconductor structure from the principal surface and adjoining the first end of the drift region, wherein the highly-doped region has a thickness greater than the drift region.

According to one embodiment, a semiconductor device includes first to fourth electrodes, a main element region, a fifth semiconductor region, a sense element region, an eighth semiconductor region, and a ninth semiconductor region. The main element region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a first gate electrode. The sense element region includes the first semiconductor region, the second semiconductor region, a sixth semiconductor region, a seventh semiconductor region, and a second gate electrode. An area of the sense element region in the first plane is smaller than an area of the main element region in the first plane. The eighth semiconductor region is provided around the sense element region. The ninth semiconductor region is provided between the main element region and the sense element region, and electrically connected to the eighth semiconductor region.

A semiconductor device includes a semiconductor substrate having an upper surface and a lower surface, an element region containing a semiconductor element and a peripheral region surrounding the element region in plan view. The semiconductor substrate in the peripheral region includes an N-type drift layer, an N++ type channel stop layer disposed on the upper surface side relative to the N-type drift layer, which channel stop layer is at least one annular N++ type channel stop layer surrounding the element region, and an N type guard ring layer disposed on the upper surface side relative to the N-type drift layer.

According to one embodiment, a semiconductor device includes first to fourth electrodes, first and second terminals, a semiconductor member, and a first insulating member. The semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a fifth semiconductor region of the second conductivity type. The first insulating member includes a first insulating region and a second insulating region. The first insulating region is between the third electrode and the semiconductor member. The second insulating region is between the fourth electrode and the semiconductor member.

A semiconductor device according to an embodiment includes a transistor region, a diode region, and a termination region surrounding the transistor region and the diode region. The transistor region includes first trenches and first conductive layers in the first trenches. The diode region includes second trenches and second conductive layers in the second trenches. The termination region includes a third trench, a first electrode pad electrically connected to the first conductive layers in at least a part of the first trench, and a second electrode pad electrically connected to a second conductive layer in a second trench closest to the third trench among the second trenches.

A method of producing a power semiconductor device includes: providing a semiconductor body with a front side having a substantially horizontal area above both an active region and an edge termination region of the semiconductor body; forming, at the front side, a first insulation layer above both the active region and the edge termination region; forming, at the first insulation layer, a first mask layer that covers the edge termination region at least partially and exposes the active region; removing a portion of the first insulation layer covering the active region; and while the first mask layer or a modified first mask layer or another mask layer covers the edge termination region, subjecting the edge termination region to a first implantation processing step to form, in the edge termination region, one or more doped semiconductor regions.