A memory cell circuit is provided that may include: a memory cell, the memory cell including a ferroelectric structure; a first control terminal and a second control terminal connected to the memory cell, the first control terminal and the second control terminal being configured to allow an operation of the memory cell; and a first auxiliary terminal and a second auxiliary terminal connected to the memory cell, the first auxiliary terminal and the second auxiliary terminal being configured to provide an auxiliary voltage to the ferroelectric structure.

Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

According to various aspects, a memory cell is provided, the memory cell may include a field-effect transistor; a first control node and a second control node, a first capacitor structure including a first electrode connected to the first control node, a second electrode connected to a gate region of the field-effect transistor, and a remanent-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure; and a second capacitor structure including a first electrode connected to the second control node, a second electrode connected to the gate region of the field-effect transistor. In some aspects, the first capacitor structure may have a first capacitance and the second capacitor structure may have a second capacitance different from the first capacitance.

Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.

A memory cell circuit is provided that may include: a memory cell, the memory cell including a ferroelectric structure; a first control terminal and a second control terminal connected to the memory cell, the first control terminal and the second control terminal being configured to allow an operation of the memory cell; and a first auxiliary terminal and a second auxiliary terminal connected to the memory cell, the first auxiliary terminal and the second auxiliary terminal being configured to provide an auxiliary voltage to the ferroelectric structure.

An integrated circuit construction comprising memory comprises two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section. The two memory-cell-array regions individually comprise a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between. A laterally-extending insulator structure is about lateral peripheries of the capacitor storage node electrodes and is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section. The peripheral-circuitry region in the vertical cross-section comprises a pair of elevationally-extending walls comprising a first insulative composition. A second insulative composition different from the first insulative composition is laterally between the pair of walls. The pair of walls individually have a laterally-outer side of the first insulative composition that is directly against a lateral edge of the insulator structure that is in different ones of the two array regions. Other embodiments, including methods, are disclosed.

An integrated circuit construction comprising memory comprises two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section. The two memory-cell-array regions individually comprise a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between. A laterally-extending insulator structure is about lateral peripheries of the capacitor storage node electrodes and is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section. The peripheral-circuitry region in the vertical cross-section comprises a pair of elevationally-extending walls comprising a first insulative composition. A second insulative composition different from the first insulative composition is laterally between the pair of walls. The pair of walls individually have a laterally-outer side of the first insulative composition that is directly against a lateral edge of the insulator structure that is in different ones of the two array regions. Other embodiments, including methods, are disclosed.

A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.