A p-GaN gate tunnel junction HEMT includes a nucleation layer, buffer layer, nitride-based channel layer, nitride-based barrier layer, p-type GaN layer, gate electrode, source electrode, drain electrode, and surface passivation layer. The nucleation and buffer layers are disposed on a substrate, with the nitride-based channel layer above. The nitride-based barrier layer is positioned on the nitride-based channel layer, creating a 2DEG channel between the channel and barrier layers. The p-type GaN layer is positioned on the nitride-based barrier layer. The gate electrode is positioned on the p-type GaN layer. The source electrode forms a tunnel junction with the 2DEG channel, and the drain electrode is placed on the nitride-based barrier layer. The passivation layer covers the nitride-based barrier layer with portions between the gate-source and gate-drain regions.

A semiconductor device including a HEMT using an N polar plane has a semiconductor laminated structure including a base layer, a barrier layer, and a channel layer. The base layer has a first surface, which is a (000-1) plane, and contains AlN. The barrier layer is formed on the first surface side of the base layer where the first surface is provided, contains AlGaN, and is lattice-relaxed with respect to the base layer. The channel layer is formed on a second surface side of the barrier layer and contains GaN. The barrier layer is not lattice-matched with but is lattice-relaxed with respect to the base layer, and the channel layer is lattice-matched with the barrier layer.

A heterostructure includes a substrate and a layer stack of layer pairs on the substrate. The heterostructure may be part of a field-effect transistor or light emitting device, such as a laser, an LED, or a quantum cascade emitter. Each of the layer pairs includes (i) a first nitride layer that includes a metal and (ii) a second nitride layer that includes aluminum and gallium. A material composition of the first nitride layer may be Al.sub.1-xM.sub.xN, where x is between 0.01 and 0.18, inclusive, and M includes one or more of a group-III element, a rare earth element, boron, and gallium. A material composition of the second nitride layer may be Al.sub.1-yGa.sub.yN, where y is between 0.85 and 1.0, inclusive.

A nitride semiconductor transistor includes a barrier layer including a first top surface having nitrogen polarity; a channel layer located over the first top surface and including a second top surface having the nitrogen polarity, the channel layer having a first polarization in a first direction; and a ferroelectric layer located over the second top surface and having a second polarization in a second direction opposite to the first direction.

A nitride semiconductor transistor includes a first channel layer having a first upper surface with a nitrogen polarity; a ferroelectric nitride semiconductor layer deposited on the first upper surface and having a second upper surface with a first metal polarity; a second channel layer deposited on the second upper surface and having a third upper surface with a second metal polarity; and a first barrier layer deposited on the third upper surface and having a fourth upper surface with a third metal polarity.