A semiconductor device may include a substrate, a lower power line in a lower portion of the substrate, metal layers on the substrate, and a protection structure that is electrically connected to the lower power line and the metal layers. The protection structure may include a doping pattern in the substrate, and a first source/drain pattern that is on the substrate and is electrically connected to an upper portion of the doping pattern. The doping pattern and the first source/drain pattern may include different dopants from each other.

A semiconductor device includes: a substrate; source/drain patterns on the substrate; a channel pattern between the source/drain patterns, the channel pattern including a plurality of semiconductor patterns; a gate electrode between the plurality of semiconductor patterns; an upper separation structure extending in a first direction and spaced apart from the gate electrode in a second direction intersecting the first direction; a first backside separation structure penetrating the substrate below the gate electrode in a third direction intersecting the first direction and the second direction; and a second backside separation structure penetrating the substrate and overlapping the upper separation structure in the third direction.

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes alternatingly stacked first semiconductor layers and second semiconductor layers. The method also includes laterally recessing the first semiconductor layers of the fin structure to form a plurality of notches, forming a plurality of inner spacers in the notches, laterally recessing the inner spacers to form a plurality of recesses in the inner spacers, and growing a source/drain feature over the fin structure. The recesses are sealed by the source/drain feature and the inner spacers to form a plurality of air spacers.

A semiconductor device may include high-integrated memory cells, and a method for fabricating the semiconductor device may include forming a plurality of preliminary nano sheets disposed with first horizontal gaps therebetween over a substrate, forming a spacer layer surrounding portions of the preliminary nano sheets and defines second horizontal gaps between the preliminary nano sheets, forming gap-fill layers that fill the second horizontal gaps of the spacer layer, forming inter-cell dielectric layers on the gap-fill layers and the spacer layer, horizontally recessing the gap-fill layers and the spacer layer and forming a linear surrounding recess, and forming a conductive line horizontally extending while surrounding portions of the preliminary nano sheets in the linear surrounding recess.

An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.

The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.