An integrated circuit includes a substrate member having a surface region and a CMOS IC layer overlying the surface region. The CMOS IC layer has at least one CMOS device. The integrated circuit also includes a bottom isolation layer overlying the CMOS IC layer, a shielding layer overlying a portion of the bottom isolation layer, and a top isolation layer overlying a portion of the bottom isolation layer. The bottom isolation layer includes an isolation region between the top isolation layer and the shielding layer. The integrated circuit also has a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer. The MEMS layer includes at least one MEMS structure having at least one movable structure and at least one anchored structure. The at least one anchored structure is coupled to a portion of the top isolation layer, and the at least one movable structure overlies the shielding layer.

A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap array includes a sheet resistor and an array of arcing electrode pairs formed over a substrate. The array of arcing electrode pairs includes first arcing electrodes formed on the sheet resistor and a second arcing electrode arranged as a sheet formed over the first arcing electrodes and separated from the first arcing electrodes by an arcing gap. The first arcing electrodes and second arcing electrode are electrically connected to first and second voltage nodes, respectively, and the arcing electrode pairs are configured to generate arc discharges in response to an EOS voltage signal received between the first and second voltage nodes.

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap device includes first and second conductive layers formed over a substrate, where the first and second conductive layers are electrically connected to first and second voltage nodes, respectively. The first conductive layer includes a plurality of arcing tips configured to form arcing electrode pairs with the second conductive layer to form an arc discharge in response to an EOS voltage between the first and second voltage nodes. The spark gap device further includes a series ballast resistor electrically connected between the arcing tips and the first voltage node, where the ballast resistor in formed in a metallization layer over the substrate and a resistance of the series ballast resistor is substantially higher than a resistance of the second conductive layer.

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface, a first conductive layer and a second conductive layer each extending over the substrate and substantially parallel to the horizontal main surface while being separated in a vertical direction crossing the horizontal main surface. One of the first and second conductive layers is electrically connected to a first voltage node and the other of the first and second conductive layers is electrically connected to a second voltage node. The first and second conductive layers serve as one or more arcing electrode pairs and have overlapping portions configured to generate one or more arc discharges extending generally in the vertical direction in response to an EOS voltage signal received between the first and second voltage nodes.

A MEMS device is provided that includes a piezoelectric element including a piezoelectric membrane including a ferroelectric and configured to vibrate based on an application of a voltage. A device may include a diode portion electrically connected in parallel to the piezoelectric element and including a diode.

A variable capacitance device that includes a semiconductor substrate, a redistribution layer disposed on a surface of the semiconductor substrate, and a plurality of terminal electrodes including first and second input/output terminals, a ground terminal and a control voltage application terminal. Moreover, a variable capacitance element section is formed in the redistribution layer from a pair of capacitor electrodes connected to the first and second input/output terminals, respectively, and a ferroelectric thin film disposed between the capacitor electrodes. Further, an ESD protection element is connected between the one of the input/output terminals and the ground terminal is formed on the surface of the semiconductor substrate.

A variable capacitance device that includes a semiconductor substrate, a redistribution layer disposed on a surface of the semiconductor substrate, and a plurality of terminal electrodes including first and second input/output terminals, a ground terminal and a control voltage application terminal. Moreover, a variable capacitance element section is formed in the redistribution layer from a pair of capacitor electrodes connected to the first and second input/output terminals, respectively, and a ferroelectric thin film disposed between the capacitor electrodes. Further, an ESD protection element is connected between the one of the input/output terminals and the ground terminal is formed on the surface of the semiconductor substrate.

Disclosed are a micro-electromechanical system (MEMS) structure and an MEMS microphone comprising same. The MEMS structure comprises a back plate; and a diaphragm located on one side of the back plate, wherein the diaphragm and the back plate forms a variable capacitor, the diaphragm comprises multiple first through holes and air release structures respectively corresponding to the first through holes, and the diaphragm further comprises one or more second through holes penetrating through the diaphragm.

A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800 C. to 820 C.