B81B7/0025

Hydrogen barriers in a copper interconnect process

A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen; forming a conducting hydrogen barrier over at least the exposed portion of the electrical contact; and forming a copper pillar over the conducting hydrogen barrier. In one embodiment, the material susceptible to degradation is lead zirconate titanate (PZT) and the microelectronic systems device is a ferroelectric random access memory including a ferroelectric capacitor with a PZT ferroelectric layer. Other embodiments are also disclosed.

MICROMECHANICAL LAYER SYSTEM

A micromechanical layer system, having at least two mechanically active functional layers patterned independently of each other, which are arranged vertically one on top of the other and are functionally coupled to each other.

Microfluidic passage with protective layer

A microfluidic die may include a microfluidic passage and a protective layer provided adjacent to internal surfaces of the microfluidic passage. The protective layer may include a protective nano-crystalline material and a protective amorphous matrix encapsulating the protective nano-crystalline material.

CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION
20170066648 · 2017-03-09 ·

A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.

LOW STRESS PACKAGING FOR ENVIRONMENTAL SENSORS
20250085182 · 2025-03-13 ·

One or more sensor devices are encapsulated on a top surface of a carrier substrate within an elastomer material. The carrier substrate includes one or more recessed channels adjacent to each sensor device which are filled by a portion of the elastomer material to create flanged areas that are level with the top surface of the carrier substrate. A cover which can include a liquid or gas input port or other related structures can be placed over each sensor device and bonded to the carrier substrate at the flanged areas, creating a seal between the cover and the carrier substrate that surrounds each sensor device.

RELEASE CHEMICAL PROTECTION FOR INTEGRATED COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) AND MICRO-ELECTRO-MECHANICAL (MEMS) DEVICES
20170015547 · 2017-01-19 ·

Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

MICROMECHANICAL COMPONENT AND CORRESPONDING PRODUCTION METHOD

A micromechanical component and a corresponding production method. The micromechanical component is equipped with a substrate, a function chip which is attached to the substrate and has a main surface facing away from the substrate, wherein one or more bond pads are provided on the main surface, which are bonded to the substrate by a respective bond wire. On the main surface or above the main surface of the function chip, a cover chip, which is formed from a chip material that has a diffusion-inhibiting effect on halogen ions located in the mold compound, is attached as a diffusion barrier to a mold package. The cover chip covers the main surface substantially completely. The micromechanical component further includes the mold package, in which the function chip is packaged together with the cover chip.

CHEMICAL STOP STRUCTURES FOR MEMS DEVICES
20250236514 · 2025-07-24 ·

In a micro-electromechanical system (MEMS) structure, at least one chemical stop structure is formed to reduce inadvertent etching of adhesion layers. A first adhesion layer and a second adhesion layer are separated by a primary dielectric layer. The primary dielectric layer includes a recess that forms a stair. The second adhesion layer includes an annular opening, and a protective material covers the sides of the second adhesion layer in the annular opening. A base plate layer covers the second adhesion layer and fills the recess and the annular opening. An annular via passes through the base plate layer and the protective material down to the primary dielectric layer. The protective material and the base plate layer each act as chemical stop structures that separate the first adhesion layer from the second adhesion layer.

Semiconductor devices and related methods

In one example, an electronic device can comprise (a) a first substrate comprising a first encapsulant extending from the first substrate bottom side to the first substrate top side, and a first substrate interconnect extending from the substrate bottom side to the substrate top side and coated by the first encapsulant, (b) a first electronic component embedded in the first substrate and comprising a first component sidewall coated by the first encapsulant, (c) a second electronic component coupled to the first substrate top side, (d) a first internal interconnect coupling the second electronic component to the first substrate interconnect, and (e) a cover structure on the first substrate and covering the second component sidewall and the first internal interconnect. Other examples and related methods are also disclosed herein.

Barrier structure within a microelectronic enclosure

A device includes a first substrate. The device also includes a barrier structure including a metallic layer on the first substrate, where the barrier structure forms a cavity. The device also includes a second substrate on the metallic layer, where the metallic layer extends between the first substrate and the second substrate, and where the metallic layer includes a sloped edge that contacts the first substrate within the cavity.