Described herein is a MEMS force sensor with stress concentration design. The stress concentration can be performed by providing slots, whether through or blind, and/or selective thinning of the substrate. The MEMS force sensor is in chip scale package with solder bumps or metal pillars and there are sensing elements formed on the sensor substrate at the stress concentrate area. The stress concentration can be realized through slots, selective thinning and a combination of both.

A die attachment to a support is disclosed. In an embodiment, a semiconductor package includes a support and a die attached to the support by an adhesive on a backside of the die, wherein the die includes a capacitive pressure sensor integrated on a CMOS read-out circuit, and wherein the adhesive covers only a part of the backside of the die.

An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

An electronic apparatus includes a semiconductor package including a sensor unit that outputs a signal responding to an applied physical quantity, mounted on a mounting member. An island projected region is defined as a region in the mounting member obtained by projecting an outline of an island on which the sensor unit is mounted, and a part of or entire of the island projected region is configured as a through hole or a concave portion.

The present disclosure relates to a microelectromechanical systems (MEMS) apparatus. The MEMS apparatus includes a base substrate and a conductive routing layer disposed over the base substrate. A bump feature is disposed directly over the conductive routing layer. Opposing outermost sidewalls of the bump feature are laterally between outermost sidewalls of the conductive routing layer. A MEMS substrate is bonded to the base substrate and includes a MEMS device directly over the bump feature. An anti-stiction layer is arranged on one or more of the bump feature and the MEMS device.

A cavity type semiconductor package with a substrate and a cap is disclosed. The semiconductor package includes a first semiconductor die coupled to the substrate and a layer of flexible material on a surface of the cap. A trace is on the layer of flexible material. The cap is coupled to the substrate with the layer of flexible material and the trace between the cap and the substrate. A second semiconductor die is coupled to the layer of flexible material and the trace on the cap. The cap further includes an aperture to expose the second semiconductor die to the ambient environment. The layer of flexible material absorbs stress during operation cycles of the package induced by the different coefficient of thermal expansions of the cap and the substrate to reduce the likelihood of separation of the cap from the substrate.

MEMS device formed in a semiconductor body which is monolithic and has a first and a second main surface. A buried cavity extends into the semiconductor body below and at a distance from the first main surface. A diaphragm extends between the buried cavity and the first main surface of the semiconductor body and has a buried face facing the buried cavity. A diaphragm insulating layer extends on the buried face of the diaphragm and a lateral insulating region extends into the semiconductor body along a closed line, between the first main surface and the diaphragm insulating layer, above the buried cavity. The lateral insulating region laterally delimits the diaphragm and forms, with the diaphragm insulating layer, a diaphragm insulating region which delimits the diaphragm and electrically insulates it from the rest of the wafer.

The present disclosure is directed to at least one embodiment of a die including a sidewall having a uniform surface and an irregular surface. The uniform surface may be a scalloped surface and scallops of the scalloped surface are substantially the same size and shape relative to each other. The irregular surface has a more irregular texture as compared to the uniform surface. The irregular surface may include a plurality of randomly spaced high points and a plurality of randomly spaced low points that are between adjacent ones of the high points. In a method of manufacturing the die, a cavity is pre-formed in a substrate and a multilayer structure is formed on the substrate. The multilayer structure includes an active area that is aligned with and overlies the cavity. After the multilayer structure is formed, at least one recess is formed extending into the multilayer structure to the cavity. Forming the recess forms a die structure suspended above the cavity and an extension extending from the die structure to a suspension structure surrounding the die structure. The die structure is released from the die suspension structure by breaking the extension.

A pressure sensor including: a structure which delimits a main cavity of a closed type, the structure being at least partially deformable as a function of a pressure external to the structure; and a MEMS device, which is arranged in the main cavity and generates an output signal, which is of an electrical type and is indicative of the pressure inside the main cavity.

A sensor assembly including a capacitive sensor, like a microelectromechanical (MEMS) microphone, and an electrical circuit therefor are disclosed. The electrical circuit includes a first transistor having an input gate connectable to the capacitive sensor, a second transistor having an input gate coupled to an output of the first transistor, a feedforward circuit interconnecting a back-gate of the second transistor and the output of the first transistor, and a filter circuit interconnecting the output of the first transistor and the input gate of the second transistor.