An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.

A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.

A MEMS support structure and a cap structure are provided. At least one vertically-extending trench is formed into the MEMS support structure or a portion of the cap structure. A vertically-extending outgassing material portion having a surface that is physically exposed to a respective vertically-extending cavity is formed in each of the at least one vertically-extending trench. A matrix material layer is attached to the MEMS support structure. A movable element laterally confined within a matrix layer is formed by patterning the matrix material layer. The matrix layer is bonded to the cap structure. A sealed chamber containing the movable element is formed. Each vertically-extending outgassing material portion has a surface that is physically exposed to the sealed chamber, and outgases a gas to increase the pressure in the sealed chamber.

Microelectromechanical system (MEMS) devices, methods of operating the MEMS device, and methods of manufacturing the MEMS device are disclosed. In some embodiments, the MEMS device includes a glass substrate; an electrode on the glass substrate; a hinge mechanically coupled to the electrode; a membrane mirror mechanically coupled to the hinge; a TFT on the glass substrate and electrically coupled to the electrode; and a control circuit comprising: a multiplexer configured to turn on or turn off the TFT; and a drive source configured to provide a drive signal for charging the electrode through the TFT. An amplitude of the drive signal corresponds to an amount of charge, and the amount of charge generates an electrostatic force for actuating the hinge and a portion of the membrane mirror mechanically coupled to the hinge.

The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate. A micro-electromechanical system (MEMS) layer overlies the semiconductor device substrate. The MEMS layer includes a first moveable mass and a second moveable mass. A capping layer overlies the MEMS layer. The capping layer has a first lower surface directly over the first moveable mass and a second lower surface directly over the second moveable mass. An outgas layer is on the first lower surface and directly between the first pair of sidewalls. A lower surface of the outgas layer delimits a first cavity in which the first moveable mass is arranged. The second lower surface of the capping layer delimits a second cavity in which the second moveable mass is arranged.

Aspects of the invention relate to a semiconductor chip comprising a substrate and a stack arranged on the substrate. The stack comprises one or more insulating layers and one or more metal layers. The chip comprises a sensor device arranged in a sensor area (SA) of the semiconductor chip and processing circuitry arranged in a processing area (PA) of the semiconductor chip. The chip further comprises connection circuitry configured to provide an electrical connection between the sensor device and the processing circuitry. A first seal ring structure is arranged between an outer edge (ED) of the chip and an inner area (IA) of the chip. The inner area (IA) of the chip encompasses the sensor area (SA) and the processing area (PA). A second seal ring structure is arranged between the sensor area (SA) and the processing area (PA) and configured to constrain an infiltration of contaminants from the sensor area (SA) to the processing area (PA).

A semiconductor device comprising a first and second doped semiconductor layer wherein the first layer is a monosilicon layer and the second layer is a polysilicon layer, an oxide layer covering the first and second layer, and an interconnect which electrically connects the first and second layer comprises a metal alloy which has a first part in contact with the first layer and a second part in contact with the second layer, wherein a part of the metal alloy between the first and the second part crosses over a sidewall of the second layer; at least one electronic component is formed in the first and/or second layer; the semiconductor device moreover comprises a stoichiometric passivation layer which covers the first and second layer and the oxide layer.

A monolithic integrated device may include a first device having a complementary metal-oxide-semiconductor (CMOS) substrate, and a second device arranged over the CMOS substrate. The second device may include a first conductive element, and a second conductive element arranged over the first conductive element. A via opening may extend through the first conductive element and the second conductive element of the second device to an interconnect of the CMOS substrate. A via contact may be arranged in the via opening to contact the first conductive element, the second conductive element, and the interconnect of the CMOS substrate. The via contact electrically connects the first conductive element and the second conductive element of the second device to the interconnect of the CMOS substrate.

CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

An optical electronics device includes first, second and third wafers. The first wafer has a semiconductor substrate with a dielectric layer on a side of the semiconductor substrate. The second wafer has a transparent substrate with an anti-reflective coating on a side of the transparent substrate. The first wafer is bonded to the second wafer at a silicon dioxide layer between the semiconductor substrate and the anti-reflective coating. The first and second wafers include a cavity extending from the dielectric layer through the semiconductor substrate and through the silicon dioxide layer to the anti-reflective coating. The third wafer includes micromechanical elements. The third wafer is bonded to the dielectric layer, and the micromechanical elements are contained within the cavity.